CY7C63310, CY7C638xx
Figure 16-4. 16-Bit Free Running Counter Loading Timing Diagram
clk_sys
write
valid
addr
write data
FRT reload ready
Clk Timer
12b Prog Timer
12b reload
interrupt
Capture timer
clk
16b free running
counter load
16b free | 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0 | |
running counter | ||
|
Figure 16-5. Memory Mapped Registers Read/Write Timing Diagram
clk_sys
rd_wrn
Valid
Addr
rdata
wdata
Document | Page 49 of 83 |
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