Cypress CY7C638xx manual Clock Architecture Description, Iosc Trim Iosctr 0x34 R/W, Bit 40 Gain

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CY7C63310, CY7C638xx

10.1 Clock Architecture Description

The enCoRe II clock selection circuitry allows the selection of independent clocks for the CPU, USB, Interval Timers and Capture Timers.

The CPU clock CPUCLK is sourced from an external clock or the Internal 24 MHz Oscillator. The selected clock source is optionally divided by 2n, where n is 0-5,7 (see Table 10-4on page 23).

USBCLK, which must be 12 MHz for the USB SIE to function properly, is sourced by the Internal 24 MHz Oscillator or an external 12 MHz/24 MHz clock. An optional divide by two allows the use of 24 MHz source.

The Interval Timer clock (ITMRCLK), is sourced from an external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz low power oscillator, or from the timer capture clock (TCAPCLK). A programmable prescaler of 1, 2, 3, 4 then divides the selected source.

Table 10-1. IOSC Trim (IOSCTR) [0x34] [R/W]

The Timer Capture clock (TCAPCLK) is sourced from an external clock, Internal 24 MHz Oscillator, or the Internal 32 kHz low power oscillator.

The CLKOUT pin (P0.1) is driven from one of many sources. This is used for test and is also used in some applications. The sources that drive the CLKOUT follow:

■CLKIN after the optional EFTB filter

■Internal 24 MHz Oscillator

■Internal 32 kHz low power oscillator

■CPUCLK after the programmable divider

Bit #

7

6

5

4

3

2

1

0

Field

 

foffset[2:0]

 

 

 

Gain[4:0]

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

D

D

D

D

D

 

 

 

 

 

 

 

 

 

The IOSC Calibrate register calibrates the internal oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test. This value does not require change during normal use. This is the meaning of ‘D’ in the Default field.

Bit [7:5]: foffset [2:0]

This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and are zero. Setting each of these bits causes the appropriate fine offset in oscillator frequency.

foffset bit 0 = 7.5 kHz foffset bit 1 = 15 kHz foffset bit 2 = 30 kHz

Bit [4:0]: Gain [4:0]

The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change (kHz/offsetStep) at each bit, typical conditions (24 MHz operation):

Gain bit 0 = –1.5 kHz Gain bit 1 = –3.0 kHz Gain bit 2 = –6 kHz Gain bit 3 = –12 kHz Gain bit 4 = –24 kHz

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Contents Applications FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08Gpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Pin Description Gpio Port 1 bit 0/USB D+ 1 If this pin is used as aGpio Port 1 bit 1/USB D- 1 If this pin is used as a No connect CPU ArchitectureSupply GroundFlags Register CPU RegistersAddressing Modes Source Indexed Opcode Operand Source Direct Opcode Operand10. Destination Direct Opcode Operand Destination Indexed13. Destination Indexed Source Immediate Opcode Operand 12. Destination Direct Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryFlash Program Memory Organization Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2Flash Data Memory OrganizationSrom Stack begins here and grows upwardSrom Function Parameters Variable Name Sram Address Srom Function DescriptionsSrom Return Codes Description ReadBlock Parameters Name Address DescriptionWriteBlock Parameters Name Address Description Protection Modes Settings Description MarketingEraseBlock Parameters Name Address Description Block Block nEraseAll Parameters Name Address Description ProtectBlock Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Clocking Checksum Function12. Checksum Parameters Name Address Description Clock Block Diagram Clock Architecture Description Iosc Trim Iosctr 0x34 R/WBit 40 Gain CPU/USB Clock Config Cpuclkcr 0x30 R/W Lposc Trim Lposctr 0x36 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/WTimer Clock Config Tmrclkcr 0x31 R/W USB Osclock Clock Configuration Osclckcr 0x39 R/WBit 72 Reserved = TcapclkInterval Timer Clock Itmrclk Timer Capture Clock TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Power on Reset Sleep ModeWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 WWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeLow Voltage Control Register Lvdcr 0x1E3 R/W Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxBit 72 Reserved Bit 1 LVD Voltage Monitor Comparators Register Vltcmp 0x1E4 RECO Trim Register ECO Ecotr 0x1EB R/WGeneral Purpose IO Gpio Ports Port Data RegistersP0 Data Register P0DATA0x00 R/W P1 Data Register P1DATA 0x01 R/W P2 Data Register P2DATA 0x02 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W10. P1.0/D+ Configuration P10CR 0x0D R/W P0.7 Configuration P07CR 0x0C R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 13. P1.3 Configuration P13CR 0x10 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/WSerial Peripheral Interface SPI 17. P3 Configuration P3CR 0x16 R/WSPI Data Register SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Interface Pins SPI Mode Timing vs. LSB First, Cpol and CphaSclk Ssel DAT a Free Running Timer Low order Byte Frtmrl 0x20 R/W Timer RegistersFree Running Timer High-order Byte Frtmrh 0x21 R/W RegistersTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/WBit 74 Reserved Programmable Interval Timer High Pitmrh 0x27 RProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/WTimer Capture 11. Timer Configuration Tmrcr 0x2A R/WBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerInterrupt Trigger Conditions Interrupt ProcessingInterrupt Latency PCH PC158 is cleared to zeroInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt RegistersInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/WBit 7 Enable Software Interrupt Enswint Interrupt Mask 3 INTMSK3 0xDE R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WRegulator Output Vreg ControlVreg Control Register Vregcr 0x73 R/W USB Transceiver Configure Register Usbxcr 0x74 R/W USB Transceiver ConfigurationUSB/PS2 Transceiver USB Serial Interface Engine SIEUSB Device Address USB DeviceEndpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode Endpoint 0 Mode EP0MODE 0x44 R/WBit 30 Mode Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 1 and 2 ModeBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/WMode Column USB Mode TablesEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency CharacteristicsAbsolute Maximum Ratings DC CharacteristicsDetect 3V RegulatorGeneral Purpose IO Interface AC CharacteristicsParameter Description Conditions Min Typical Max Unit Clock CpuclkNon-USB Mode Driver Characteristics USB Data TimingSPI Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Updated part numbers in the header Added block diagrams and timing diagramsRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration detailsCMCC/PYRS VGT/AESASales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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