Cypress CY7C638xx, CY7C63310 manual Introduction, Conventions

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CY7C63310, CY7C638xx

3. Introduction

Cypress has reinvented its leadership position in the low speed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB - “enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to advance its family of low speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components. The enCoRe II USB technology builds on the enCoRe family. The enCoRe family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Also integrated into this chip are other external components commonly found in low speed USB applications, such as pull up resistors, wakeup circuitry, and a 3.3V regulator. Integrating these components reduces the overall system cost.

The enCoRe II is an 8-bit Flash programmable microcontroller with an integrated low speed USB interface. The instruction set is optimized specifically for USB and PS/2 operations, although the microcontrollers may be used for a variety of other embedded applications.

The enCoRe II features up to 20 GPIO pins to support USB, PS/2, and other applications. The IO pins are grouped into four ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2 and 3 are configured only as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support a programmable drive strength of up to 50 mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3V. Additionally, each IO pin may be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector; in addition, GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2 - P0.4).

The enCoRe II features an internal oscillator. With the presence of USB traffic, the internal oscillator may be set to precisely tune to USB timing requirements (24 MHz ±1.5%). Optionally, an external 12 MHz or 24 MHz clock is used to provide a higher precision reference for USB operation. The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller. The enCoRe II also has a 12-bit program- mable interval timer and a 16-bit Free Running Timer with Capture Timer registers. In addition, the enCoRe II includes a Watchdog timer and a vectored interrupt controller.

The enCoRe II has up to eight Kbytes of Flash for user code and up to 256 bytes of RAM for stack space and user variables.

The power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates a reset or may be configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. It is configurable to generate an LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt. There is no separate interrupt for each. The Watchdog timer may be used to ensure the firmware never gets stalled in an infinite loop.

The microcontroller supports 22 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024 ms output from the free-running timer, three USB endpoints, two capture timers, four GPIO Ports, three Port 0 pins, two SPI, a 16-bit free running timer wrap, an internal sleep timer, and a bus active interrupt. The sleep timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt when a new timer value is saved because of a selected GPIO edge event. A total of seven GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility on the edge sensitive GPIO pins, the interrupt polarity is programmed as rising or falling.

The free-running 16-bit timer provides two interrupt sources: the 1.024 ms outputs and the free running counter wrap interrupt. The programmable interval timer provides up to 1 μsec resolution and provides an interrupt every time it expires. These timers are used to measure the duration of an event under firmware control by reading the desired timer at the start and at the end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit captures may be ganged into a single 16-bit capture.

The enCoRe II includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints.

The USB D+ and D– pins are optionally used as PS/2 SCLK and SDATA signals so that products are designed to respond to either USB or PS/2 modes of operation. The PS/2 operation is supported with internal 5 KΩ pull up resistors on P1.0 (D+) and P1.1 (D–), and an interrupt to signal the start of PS/2 activity. In USB mode, the integrated 1.5 KΩ pull up resistor on D– may be controlled under firmware. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes.

The enCoRe II supports in system programming by using the D+ and D– pins as the serial programming mode interface. The programming protocol is not USB.

4. Conventions

In this data sheet, bit positions in the registers are shaded to indicate which members of the enCoRe II family implement the bits.

Available in all enCoRe II family members

CY7C638(1/2/3)3 only

Document 38-08035 Rev. *K

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Contents San Jose, CA Document 38-08035 Rev. *K Revised December 08 FeaturesApplications Cypress Semiconductor Corporation 198 Champion CourtGpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Pin Description Gpio Port 1 bit 0/USB D+ 1 If this pin is used as aGpio Port 1 bit 1/USB D- 1 If this pin is used as a Ground CPU ArchitectureNo connect SupplyFlags Register CPU RegistersAddressing Modes Destination Indexed Source Direct Opcode OperandSource Indexed Opcode Operand 10. Destination Direct Opcode Operand15. Source Indirect Post Increment Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 14. Destination Direct Source Direct Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryEP0 EP1 EP2 Memory OrganizationFlash Program Memory Organization POR/LVD INT0Stack begins here and grows upward Data Memory OrganizationFlash SromReadBlock Parameters Name Address Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address Srom Return Codes DescriptionBlock Block n Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description EraseBlock Parameters Name Address Description11. Return values for Table Read Table Number Return Value ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 10. Table Read Parameters Name Address DescriptionSrom Table Clocking Checksum Function12. Checksum Parameters Name Address Description Clock Block Diagram Clock Architecture Description Iosc Trim Iosctr 0x34 R/WBit 40 Gain CPU/USB Clock Config Cpuclkcr 0x30 R/W Lposc Trim Lposctr 0x36 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/W= Tcapclk USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W Bit 72 ReservedInterval Timer Clock Itmrclk Timer Capture Clock TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Reset Watchdog Timer Reswdt 0xE3 W Sleep ModePower on Reset Watchdog Timer ResetWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeBit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10ECO Ecotr 0x1EB R/W Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Trim RegisterGeneral Purpose IO Gpio Ports Port Data RegistersP0 Data Register P0DATA0x00 R/W P1 Data Register P1DATA 0x01 R/W P2 Data Register P2DATA 0x02 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W12. P1.2 Configuration P12CR 0x0F R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 11. P1.1/D- Configuration P11CR 0x0E R/W16. P2 Configuration P2CR 0x15 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 15. P1.7 Configuration P17CR 0x14 R/WSPI Data Register Spidata 0x3C R/W 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data RegisterSPI Configure Register SPI Interface Pins SPI Mode Timing vs. LSB First, Cpol and CphaSclk Ssel DAT a Registers Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W Free Running Timer High-order Byte Frtmrh 0x21 R/WTimer Capture 1 Falling TIO1F 0x25 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Falling TIO0F 0x24 R/W10. Programmable Interval Reload High Pirh 0x29 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved Programmable Interval Reload Low Pirl 0x28 R/WTimer Capture 11. Timer Configuration Tmrcr 0x2A R/WBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerPCH PC158 is cleared to zero Interrupt ProcessingInterrupt Trigger Conditions Interrupt LatencyInterrupt Clear 2 INTCLR2 0xDC R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 1 INTCLR1 0xDB R/WBit 7 Enable Software Interrupt Enswint Interrupt Mask 3 INTMSK3 0xDE R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WRegulator Output Vreg ControlVreg Control Register Vregcr 0x73 R/W USB Serial Interface Engine SIE USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB/PS2 TransceiverUSB Device Address Usbcr 0x40 R/W USB DeviceUSB Device Address Endpoint 0, 1, and 2 CountEndpoint 0 Mode Endpoint 0 Mode EP0MODE 0x44 R/WBit 30 Mode Endpoint 0 Data EP0DATA 0x50-0x57 R/W Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Bit 7 StallEndpoint 2 Data EP2DATA 0x60-0x67 R/W USB Mode TablesMode Column Encoding ColumnSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency Characteristics3V Regulator DC CharacteristicsAbsolute Maximum Ratings DetectCpuclk AC CharacteristicsGeneral Purpose IO Interface Parameter Description Conditions Min Typical Max Unit ClockNon-USB Mode Driver Characteristics USB Data TimingSPI Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed Gpio port 4 configuration details Added block diagrams and timing diagramsUpdated part numbers in the header Removed 638xx die diagram and die form pad assignmentCMCC/PYRS VGT/AESASales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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