Cypress
CY7C638xx, CY7C63310
manual
Pin QFN Package
DC Characteristics
Logic Block Diagram
Addr Name Default
Interval Timer Clock Itmrclk
Gpio Port Configuration
Reset
SETUP, IN, and OUT Columns
SPI Interface Pins
Low Power in Sleep Mode
Features
Page 79
CY7C63310, CY7C638xx
Figure
31-7.
32-Pin
QFN Package
51-85188-*B
Figure
31-8.
32-Pin
Sawn QFN Package
001-30999
*A
Document
38-08035
Rev. *K
Page 79 of 83
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Contents
San Jose, CA Document 38-08035 Rev. *K Revised December 08
Features
Applications
Cypress Semiconductor Corporation 198 Champion Court
Gpio
Logic Block Diagram
Conventions
Introduction
Pinouts
Die Pad Summary Pad Number Pad Name Microns
Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a
Pin Description
Gpio Port 1 bit 1/USB D- 1 If this pin is used as a
Ground
CPU Architecture
No connect
Supply
Flags Register
CPU Registers
Addressing Modes
Destination Indexed
Source Direct Opcode Operand
Source Indexed Opcode Operand
10. Destination Direct Opcode Operand
15. Source Indirect Post Increment Opcode Operand
12. Destination Direct Source Immediate Opcode Operand
13. Destination Indexed Source Immediate Opcode Operand
14. Destination Direct Source Direct Opcode Operand
Instruction Set Summary Sorted Numerically by Opcode Order2
Instruction Set Summary
EP0 EP1 EP2
Memory Organization
Flash Program Memory Organization
POR/LVD INT0
Stack begins here and grows upward
Data Memory Organization
Flash
Srom
ReadBlock Parameters Name Address Description
Srom Function Descriptions
Srom Function Parameters Variable Name Sram Address
Srom Return Codes Description
Block Block n
Protection Modes Settings Description Marketing
WriteBlock Parameters Name Address Description
EraseBlock Parameters Name Address Description
11. Return values for Table Read Table Number Return Value
ProtectBlock Parameters Name Address Description
EraseAll Parameters Name Address Description
10. Table Read Parameters Name Address Description
Srom Table
Checksum Function
Clocking
12. Checksum Parameters Name Address Description
Clock Block Diagram
Iosc Trim Iosctr 0x34 R/W
Clock Architecture Description
Bit 40 Gain
Lposc Trim Lposctr 0x36 R/W
CPU/USB Clock Config Cpuclkcr 0x30 R/W
Bit 41 Reserved
Bit 76 Reserved Bit 5 No Buzz
OSC Control 0 OSCCR0 0x1E0 R/W
= Tcapclk
USB Osclock Clock Configuration Osclckcr 0x39 R/W
Timer Clock Config Tmrclkcr 0x31 R/W
Bit 72 Reserved
Timer Capture Clock Tcapclk
Interval Timer Clock Itmrclk
Cou nte r Terru pt Ntro ller Document 38-08035 Rev. *K
Clock IO Config Clkiocr 0x32 R/W
CPU Clock During Sleep Mode
Reset
Reset Watchdog Timer Reswdt 0xE3 W
Sleep Mode
Power on Reset
Watchdog Timer Reset
Wake up Sequence
Sleep Sequence
Wake Up Timing
Low Power in Sleep Mode
Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max
Low Voltage Detect Control
Low Voltage Control Register Lvdcr 0x1E3 R/W
Bit 76 Reserved Bit 54 PORLEV10
ECO Ecotr 0x1EB R/W
Voltage Monitor Comparators Register Vltcmp 0x1E4 R
Bit 72 Reserved Bit 1 LVD
ECO Trim Register
Port Data Registers
General Purpose IO Gpio Ports
P0 Data Register P0DATA0x00 R/W
P2 Data Register P2DATA 0x02 R/W
P1 Data Register P1DATA 0x01 R/W
P3 Data Register P3DATA 0x03 R/W
Gpio Port Configuration
P0.1/CLKOUT Configuration P01CR 0x06 R/W
P0.0/CLKIN Configuration P00CR 0x05 R/W
P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W
P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W
12. P1.2 Configuration P12CR 0x0F R/W
P0.7 Configuration P07CR 0x0C R/W
10. P1.0/D+ Configuration P10CR 0x0D R/W
11. P1.1/D- Configuration P11CR 0x0E R/W
16. P2 Configuration P2CR 0x15 R/W
13. P1.3 Configuration P13CR 0x10 R/W
14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W
15. P1.7 Configuration P17CR 0x14 R/W
SPI Data Register Spidata 0x3C R/W
17. P3 Configuration P3CR 0x16 R/W
Serial Peripheral Interface SPI
SPI Data Register
SPI Configure Register
SPI Mode Timing vs. LSB First, Cpol and Cpha
SPI Interface Pins
Sclk Ssel DAT a
Registers
Timer Registers
Free Running Timer Low order Byte Frtmrl 0x20 R/W
Free Running Timer High-order Byte Frtmrh 0x21 R/W
Timer Capture 1 Falling TIO1F 0x25 R/W
Timer Capture 0 Rising TIO0R 0x22 R/W
Timer Capture 1 Rising TIO1R 0x23 R/W
Timer Capture 0 Falling TIO0F 0x24 R/W
10. Programmable Interval Reload High Pirh 0x29 R/W
Programmable Interval Timer High Pitmrh 0x27 R
Bit 74 Reserved
Programmable Interval Reload Low Pirl 0x28 R/W
11. Timer Configuration Tmrcr 0x2A R/W
Timer Capture
Bit 20 Reserved
13. Capture Interrupt Status Tcapints 0x2C R/W
12. Capture Interrupt Enable Tcapinte 0x2B R/W
Timer Functional Sequence Diagram
Bit Free Running Counter Loading Timing Diagram
Architectural Description
Interrupt Controller
PCH PC158 is cleared to zero
Interrupt Processing
Interrupt Trigger Conditions
Interrupt Latency
Interrupt Clear 2 INTCLR2 0xDC R/W
Interrupt Registers
Interrupt Clear 0 INTCLR0 0xDA R/W
Interrupt Clear 1 INTCLR1 0xDB R/W
Interrupt Mask 3 INTMSK3 0xDE R/W
Bit 7 Enable Software Interrupt Enswint
Bit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W
Interrupt Mask 1 INTMSK1 0xE1 R/W
Interrupt Vector Clear Register Intvc 0xE2 R/W
Interrupt Mask 0 INTMSK0 0xE0 R/W
Vreg Control
Regulator Output
Vreg Control Register Vregcr 0x73 R/W
USB Serial Interface Engine SIE
USB Transceiver Configuration
USB Transceiver Configure Register Usbxcr 0x74 R/W
USB/PS2 Transceiver
USB Device Address Usbcr 0x40 R/W
USB Device
USB Device Address
Endpoint 0, 1, and 2 Count
Endpoint 0 Mode EP0MODE 0x44 R/W
Endpoint 0 Mode
Bit 30 Mode
Endpoint 0 Data EP0DATA 0x50-0x57 R/W
Endpoint 1 and 2 Mode
Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W
Bit 7 Stall
Endpoint 2 Data EP2DATA 0x60-0x67 R/W
USB Mode Tables
Mode Column
Encoding Column
SETUP, IN, and OUT Columns
Details of Mode for Differing Traffic Conditions
Count Fifo
Register Summary
Addr Name Default
Tmrcr
Intvc
Voltage vs CPU Frequency Characteristics
Voltage Vs CPU Frequency Characteristics
3V Regulator
DC Characteristics
Absolute Maximum Ratings
Detect
Cpuclk
AC Characteristics
General Purpose IO Interface
Parameter Description Conditions Min Typical Max Unit Clock
USB Data Timing
Non-USB Mode Driver Characteristics
SPI Timing
Clock Timing
Gpio Timing Diagram
Differential Data Lines
SCK CPOL=0
SCK CPOL=0 SCK CPOL=1
Package Handling
Ordering Information
Pin 300-Mil Molded DIP P1
Package Diagrams
Pin 300-Mil Molded DIP P3
Pin 300-Mil Soic S13
Pin QFN Package
Document History
Removed Gpio port 4 configuration details
Added block diagrams and timing diagrams
Updated part numbers in the header
Removed 638xx die diagram and die form pad assignment
CMCC/PYRS
VGT/AESA
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