Cypress CY7C638xx, CY7C63310 manual Voltage Vs CPU Frequency Characteristics

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CY7C63310, CY7C638xx

25. Voltage Vs CPU Frequency Characteristics

Figure 25-1. Voltage vs CPU Frequency Characteristics

 

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p a

 

 

 

 

 

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(volts)

 

R er

 

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d

 

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4.75

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io

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Vdd

 

 

 

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4.00

 

 

 

 

 

 

 

93 KHz

 

 

 

12 MHz 24 MHz

CPU Frequency

Running the CPU at 24 MHz requires a minimum voltage of 4.75V. This applies to any CPU speed above 12 MHz, so using an external clock between 12 - 24 MHz must also adhere to this requirement. Operating the CPU at 24MHz when the supply voltage is below 4.75V can cause undesired behavior and must be avoided.

Many enCoRe II applications use USB Vbus 5V as the power source for the device. According to the USB specification, voltage can be less than 4.75V on Vbus (if the USB port is a low power port the voltage can be between 4.4V and 5.25V). Even for externally powered 5V applications, developers must consider that on power up and power down voltage is less than 4.75V for some time. Firmware must be implemented properly to prevent undesired behavior.

Use of 24 MHz requires the use of the high POR trip point of approximately 4.55 - 4.65V (Register LVDCR 0x1E3, PORLEV[1:0] = 10b). This setting is sufficient to protect the device from problems due to operating at low voltage with CPU speeds above 12 MHz. This must be set before setting the CPU speed to greater than 12 MHz. For devices with slow power ramps, changing the POR threshold to the high level may result in one or more resets of the device as power ramps through the chip default POR set point of approximately 2.6V up through the high POR set point.

If multiple resets are undesirable for slow power ramps, then firmware must do the following:

■Set the Low Voltage Detection circuit (Register LVDCR 0x1E3, VM[2:0]) for one of the set points above the POR (VM[2:0] = 110b ~4.73V or 111b ~4.82V).

■Monitor the LVD until voltage is above the trip point (Register VLTCMP 0x1E4, bit 1 is clear).

■Debounce the indication to ensure that voltage is above the set point for possible noisy supplies.

■Set the POR to the high set point.

■Shift CPU speed to 24 MHz.

If the supply voltage dips below 4.75V and the application can tolerate running at a CPU speed of 12 MHz, then application firmware may also implement the following to minimize the chance of a reset event due to a voltage transient:

■Set the LVD for one of the desired high setting (~4.73V or ~4.82V).

■Enable the LVD interrupt.

■In the LVD ISR, reduce CPU speed to 12 MHz and shift the POR to a lower threshold.

■Firmware can monitor for VLTCMP to clear within the normal application main loop.

■Debounce the indication to ensure voltage is above the set point.

■Shift the POR to the high set point.

■Shift the CPU to 24 MHz.

Document 38-08035 Rev. *K

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Contents San Jose, CA Document 38-08035 Rev. *K Revised December 08 FeaturesApplications Cypress Semiconductor Corporation 198 Champion CourtGpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a Ground CPU ArchitectureNo connect SupplyFlags Register CPU RegistersAddressing Modes Destination Indexed Source Direct Opcode OperandSource Indexed Opcode Operand 10. Destination Direct Opcode Operand15. Source Indirect Post Increment Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 14. Destination Direct Source Direct Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryEP0 EP1 EP2 Memory OrganizationFlash Program Memory Organization POR/LVD INT0Stack begins here and grows upward Data Memory OrganizationFlash SromReadBlock Parameters Name Address Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address Srom Return Codes DescriptionBlock Block n Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description EraseBlock Parameters Name Address Description11. Return values for Table Read Table Number Return Value ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 10. Table Read Parameters Name Address DescriptionSrom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/W= Tcapclk USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W Bit 72 ReservedTimer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Reset Watchdog Timer Reswdt 0xE3 W Sleep ModePower on Reset Watchdog Timer ResetWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeBit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10ECO Ecotr 0x1EB R/W Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Trim RegisterPort Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W12. P1.2 Configuration P12CR 0x0F R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 11. P1.1/D- Configuration P11CR 0x0E R/W16. P2 Configuration P2CR 0x15 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 15. P1.7 Configuration P17CR 0x14 R/WSPI Data Register Spidata 0x3C R/W 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data RegisterSPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Registers Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W Free Running Timer High-order Byte Frtmrh 0x21 R/WTimer Capture 1 Falling TIO1F 0x25 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Falling TIO0F 0x24 R/W10. Programmable Interval Reload High Pirh 0x29 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved Programmable Interval Reload Low Pirl 0x28 R/W11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerPCH PC158 is cleared to zero Interrupt ProcessingInterrupt Trigger Conditions Interrupt LatencyInterrupt Clear 2 INTCLR2 0xDC R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 1 INTCLR1 0xDB R/WInterrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WVreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB Serial Interface Engine SIE USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB/PS2 TransceiverUSB Device Address Usbcr 0x40 R/W USB DeviceUSB Device Address Endpoint 0, 1, and 2 CountEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Endpoint 0 Data EP0DATA 0x50-0x57 R/W Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Bit 7 StallEndpoint 2 Data EP2DATA 0x60-0x67 R/W USB Mode TablesMode Column Encoding ColumnSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency Characteristics3V Regulator DC CharacteristicsAbsolute Maximum Ratings DetectCpuclk AC CharacteristicsGeneral Purpose IO Interface Parameter Description Conditions Min Typical Max Unit ClockUSB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed Gpio port 4 configuration details Added block diagrams and timing diagramsUpdated part numbers in the header Removed 638xx die diagram and die form pad assignmentCMCC/PYRS VGT/AESAWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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