Cypress CY7C63310, CY7C638xx manual Interrupt Controller, Architectural Description

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CY7C63310, CY7C638xx

17. Interrupt Controller

The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II devices. The registers associated with the interrupt controller allow disabling interrupts globally or individually. The registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts.

The following table lists all interrupts and the priorities that are available in the enCoRe II devices.

Table 17-1. Interrupt Numbers, Priorities, Vectors

Interrupt

Interrupt

Name

Priority

Address

 

0

0000h

Reset

 

 

 

1

0004h

POR/LVD

 

 

 

2

0008h

INT0

 

 

 

3

000Ch

SPI Transmitter Empty

 

 

 

4

0010h

SPI Receiver Full

 

 

 

5

0014h

GPIO Port 0

 

 

 

6

0018h

GPIO Port 1

 

 

 

7

001Ch

INT1

 

 

 

8

0020h

EP0

 

 

 

9

0024h

EP1

 

 

 

10

0028h

EP2

 

 

 

11

002Ch

USB Reset

 

 

 

12

0030h

USB Active

 

 

 

13

0034h

1 mS Interval timer

 

 

 

14

0038h

Programmable Interval Timer

 

 

 

15

003Ch

Timer Capture 0

 

 

 

16

0040h

Timer Capture 1

 

 

 

17

0044h

16-bit Free Running Timer Wrap

 

 

 

18

0048h

INT2

 

 

 

19

004Ch

PS2 Data Low

 

 

 

20

0050h

GPIO Port 2

 

 

 

21

0054h

GPIO Port 3

 

 

 

22

0058h

Reserved

 

 

 

23

005Ch

Reserved

 

 

 

24

0060h

Reserved

 

 

 

25

0064h

Sleep Timer

 

 

 

17.1 Architectural Description

An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 17-1.on page 51 clocking in a ‘1’. The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register.

A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate INT_MSKx register). All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which is taken by the M8C if the Global Interrupt Enable bit is set in the CPU_F register.

Disabling an interrupt by clearing its interrupt mask bit (in the INT_MSKx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. It prevents a posted interrupt from becoming pending.

Nested interrupts are accomplished by re-enabling interrupts inside an interrupt service routine. To do this, set the IE bit in the Flag Register.

A block diagram of the enCoRe II Interrupt Controller is shown in Figure 17-1.on page 51.

Document 38-08035 Rev. *K

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesApplications San Jose, CA Document 38-08035 Rev. *K Revised December 08Logic Block Diagram GpioIntroduction ConventionsPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 1/USB D- 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 0/USB D+ 1 If this pin is used as a Supply CPU ArchitectureNo connect GroundCPU Registers Flags RegisterAddressing Modes 10. Destination Direct Opcode Operand Source Direct Opcode OperandSource Indexed Opcode Operand Destination Indexed14. Destination Direct Source Direct Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2POR/LVD INT0 Memory OrganizationFlash Program Memory Organization EP0 EP1 EP2Srom Data Memory OrganizationFlash Stack begins here and grows upwardSrom Return Codes Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address ReadBlock Parameters Name Address DescriptionEraseBlock Parameters Name Address Description Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description Block Block n10. Table Read Parameters Name Address Description ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table 12. Checksum Parameters Name Address Description ClockingChecksum Function Clock Block Diagram Bit 40 Gain Clock Architecture DescriptionIosc Trim Iosctr 0x34 R/W Bit 41 Reserved CPU/USB Clock Config Cpuclkcr 0x30 R/WLposc Trim Lposctr 0x36 R/W OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No BuzzBit 72 Reserved USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W = TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Interval Timer Clock ItmrclkTimer Capture Clock Tcapclk CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/WReset Watchdog Timer Reset Sleep ModePower on Reset Reset Watchdog Timer Reswdt 0xE3 WSleep Sequence Wake up SequenceLow Power in Sleep Mode Wake Up TimingBit 76 Reserved Bit 54 PORLEV10 Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxECO Trim Register Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Ecotr 0x1EB R/WP0 Data Register P0DATA0x00 R/W General Purpose IO Gpio PortsPort Data Registers P3 Data Register P3DATA 0x03 R/W P1 Data Register P1DATA 0x01 R/WP2 Data Register P2DATA 0x02 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/WP0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W11. P1.1/D- Configuration P11CR 0x0E R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 12. P1.2 Configuration P12CR 0x0F R/W15. P1.7 Configuration P17CR 0x14 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16. P2 Configuration P2CR 0x15 R/WSPI Data Register 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data Register Spidata 0x3C R/WSPI Configure Register Sclk Ssel DAT a SPI Interface PinsSPI Mode Timing vs. LSB First, Cpol and Cpha Free Running Timer High-order Byte Frtmrh 0x21 R/W Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W RegistersTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 1 Falling TIO1F 0x25 R/WProgrammable Interval Reload Low Pirl 0x28 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved 10. Programmable Interval Reload High Pirh 0x29 R/WBit 20 Reserved Timer Capture11. Timer Configuration Tmrcr 0x2A R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural DescriptionInterrupt Latency Interrupt ProcessingInterrupt Trigger Conditions PCH PC158 is cleared to zeroInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 2 INTCLR2 0xDC R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Bit 7 Enable Software Interrupt EnswintInterrupt Mask 3 INTMSK3 0xDE R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/WVreg Control Register Vregcr 0x73 R/W Regulator OutputVreg Control USB/PS2 Transceiver USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB Serial Interface Engine SIEEndpoint 0, 1, and 2 Count USB DeviceUSB Device Address USB Device Address Usbcr 0x40 R/WBit 30 Mode Endpoint 0 ModeEndpoint 0 Mode EP0MODE 0x44 R/W Bit 7 Stall Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 0 Data EP0DATA 0x50-0x57 R/WEncoding Column USB Mode TablesMode Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WDetails of Mode for Differing Traffic Conditions SETUP, IN, and OUT ColumnsCount Fifo Addr Name Default Register SummaryTmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency CharacteristicsDetect DC CharacteristicsAbsolute Maximum Ratings 3V RegulatorParameter Description Conditions Min Typical Max Unit Clock AC CharacteristicsGeneral Purpose IO Interface CpuclkSPI Timing Non-USB Mode Driver CharacteristicsUSB Data Timing Gpio Timing Diagram Clock TimingDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package HandlingPackage Diagrams Pin 300-Mil Molded DIP P1Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed 638xx die diagram and die form pad assignment Added block diagrams and timing diagramsUpdated part numbers in the header Removed Gpio port 4 configuration detailsVGT/AESA CMCC/PYRSUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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