Cypress CY7C63310, CY7C638xx P1 Data Register P1DATA 0x01 R/W, P2 Data Register P2DATA 0x02 R/W

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CY7C63310, CY7C638xx

Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

P1.7

P1.6/SMISO

P1.5/SMOSI

P1.4/SCLK

P1.3/SSEL

P1.2/VREG

P1.1/D–

P1.0/D+

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 1 pins.

Bit 7: P1.7 Data

P1.7 only exists in the CY7C638xx.

Bit [6:3]: P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)

Besides their use as the P1.6–P1.3 GPIOs, these pins are also used for the alternate function as the SPI interface pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 14-13on page 39).

The use of the pins as the P1.6–P1.3 GPIOs and the alternate functions exist in all the enCoRe II parts. Bit 2: P1.2/VREG

On the CY7C638x3, this pin is used as the P1.2 GPIO or the VREG output. If the VREG output is enabled (Bit 0 Table 19-1on page 57 is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled.

The VREG functionality is not present in the CY7C63310 and the CY7C63801 variants. A 1 μF min, 2 μF max capacitor is required on VREG output.

Bit [1:0]: P1.1–P1.0/D– and D+

When the USB mode is disabled (Bit 7 in Table 21-1on page 58 is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins respectively. If the USB Force State bit (Bit 0 in Table 19-1) is set, the state of the D– and D+ pins are controlled by writing to the D– and D+ bits.

Table 14-3. P2 Data Register (P2DATA) [0x02] [R/W]

Bit #

7

6

5

 

4

3

2

1

 

0

Field

 

 

 

Reserved

 

 

 

P2.1–P2.0

Read/Write

-

-

-

 

-

-

-

R/W

 

R/W

Default

0

0

0

 

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

This register contains the data for Port 2. Writing to this register sets the bit values to output on output enabled pins. Reading from this register returns the current state of the Port 2 pins.

Bit [7:2]: Reserved Data [7:2]

Bit [1:0]: P2 Data [1:0]

P2.1–P2.0 only exist in the CY7C638(2/3)3.

Table 14-4. P3 Data Register (P3DATA) [0x03] [R/W]

Bit #

7

6

5

 

4

3

2

1

 

0

Field

 

 

 

Reserved

 

 

 

P3.1–P3.0

Read/Write

-

-

-

 

-

-

-

R/W

 

R/W

Default

0

0

0

 

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 3 pins.

Bit [7:2]: Reserved Data [7:2]

Bit [1:0]: P3 Data [1:0]

P3.1–P3.0 only exist in the CY7C638(2/3)3.

Document 38-08035 Rev. *K

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesApplications San Jose, CA Document 38-08035 Rev. *K Revised December 08Logic Block Diagram GpioIntroduction ConventionsPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a Supply CPU ArchitectureNo connect GroundCPU Registers Flags RegisterAddressing Modes 10. Destination Direct Opcode Operand Source Direct Opcode OperandSource Indexed Opcode Operand Destination Indexed14. Destination Direct Source Direct Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2POR/LVD INT0 Memory OrganizationFlash Program Memory Organization EP0 EP1 EP2Srom Data Memory OrganizationFlash Stack begins here and grows upwardSrom Return Codes Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address ReadBlock Parameters Name Address DescriptionEraseBlock Parameters Name Address Description Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description Block Block n10. Table Read Parameters Name Address Description ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No BuzzBit 72 Reserved USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W = TcapclkTimer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/WReset Watchdog Timer Reset Sleep ModePower on Reset Reset Watchdog Timer Reswdt 0xE3 WSleep Sequence Wake up SequenceLow Power in Sleep Mode Wake Up TimingBit 76 Reserved Bit 54 PORLEV10 Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxECO Trim Register Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Ecotr 0x1EB R/WPort Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/WP0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W11. P1.1/D- Configuration P11CR 0x0E R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 12. P1.2 Configuration P12CR 0x0F R/W15. P1.7 Configuration P17CR 0x14 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16. P2 Configuration P2CR 0x15 R/WSPI Data Register 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Free Running Timer High-order Byte Frtmrh 0x21 R/W Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W RegistersTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 1 Falling TIO1F 0x25 R/WProgrammable Interval Reload Low Pirl 0x28 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved 10. Programmable Interval Reload High Pirh 0x29 R/W11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural DescriptionInterrupt Latency Interrupt ProcessingInterrupt Trigger Conditions PCH PC158 is cleared to zeroInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 2 INTCLR2 0xDC R/WInterrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/WVreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB/PS2 Transceiver USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB Serial Interface Engine SIEEndpoint 0, 1, and 2 Count USB DeviceUSB Device Address USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Bit 7 Stall Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 0 Data EP0DATA 0x50-0x57 R/WEncoding Column USB Mode TablesMode Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WDetails of Mode for Differing Traffic Conditions SETUP, IN, and OUT ColumnsCount Fifo Addr Name Default Register SummaryTmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency CharacteristicsDetect DC CharacteristicsAbsolute Maximum Ratings 3V RegulatorParameter Description Conditions Min Typical Max Unit Clock AC CharacteristicsGeneral Purpose IO Interface CpuclkUSB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Gpio Timing Diagram Clock TimingDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package HandlingPackage Diagrams Pin 300-Mil Molded DIP P1Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed 638xx die diagram and die form pad assignment Added block diagrams and timing diagramsUpdated part numbers in the header Removed Gpio port 4 configuration detailsVGT/AESA CMCC/PYRSWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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