CY7C63310, CY7C638xx
3.3V Drive
Output Enable
Open Drain
Port Data
High Sink
Data In
TTL Threshold
Figure 14-1. Block Diagram of a GPIO
VREGVCC
VREG | VCC |
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| RUP | Data Out |
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VREG GND | VCC GND |
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Table 14-5. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Field | Reserved | Int Enable | Int Act Low | TTL Thresh | Reserved | Open Drain | Pull up Enable | Output Enable |
Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | ||
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled (Bit[0] in register CPUCLKCR Table
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts.
Table 14-6. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Field | CLK Output | Int Enable | Int Act Low | TTL Thresh | Reserved | Open Drain | Pull Up Enable | Output Enable |
Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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This pin is shared between the P0.1 GPIO use and the CLKOUT pin. When CLK output is set, the internally selected clock is sent out onto P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts. Bit 7: CLK Output
0 = The clock output is disabled.
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register (Table
Document | Page 36 of 83 |
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