CY7C63310, CY7C638xx
10.1.1 Interval Timer Clock (ITMRCLK)
The Interval Timer Clock (TITMRCLK), is sourced from an external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz Low power Oscillator, or the Timer Capture clock. A programmable prescaler of 1, 2, 3 or 4 then divides the selected source. The
1 μs resolution by default. When the down counter reaches zero, the next clock is spent reloading. The reload value is read and written while the counter is running, but the counter must not unintentionally reload when the
The parameters to be set show up on the device editor view of PSoC Designer when the enCoRe II Timer User Module is placed. The parameters are PITIMER_Source and PITIMER_Divider. The PITIMER_Source is the clock to the timer and the PITMER_Divider is the value the clock is divided by.
The interval register (PITMR) holds the value that is loaded into the PIT counter on terminal count. The PIT counter is a down counter.
The Programmable Interval Timer resolution is configurable. For example:
TCAPCLK divide by x of CPU clock (for example, TCAPCLK divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz.)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 μs.)
10.1.2 Timer Capture Clock (TCAPCLK)
The Timer Capture clock is sourced from an external clock, Internal 24 MHz Oscillator or the Internal 32 kHz Low power Oscillator. A programmable
Figure 10-2. Programmable Interval Timer Block Diagram
S yste m C lo ck
C o n figu ra tio n
S ta tu s a nd
C o ntrol
12
Clo ck T im er
12
cou nter
12
cou nte r
In terru pt
C o ntro ller
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