Cypress CY7C63310, CY7C638xx manual Pinouts

Page 4

CY7C63310, CY7C638xx

5. Pinouts

Figure 5-1. Pin Diagrams

Top View

CY7C63801, CY7C63310

16-Pin PDIP

SSEL/P1.3	1	16	P1.2
SCLK/P1.4	2	15	VCC
SMOSI/P1.5	3	14	P1.1/D–
SMISO/P1.6	4	13	P1.0/D+
TIO1/P0.6	5	12	VSS
TIO0/P0.5	6	11	P0.0
INT2/P0.4	7	10	P0.1
INT1/P0.3	8	9	P0.2/INT0

CY7C63801, CY7C63310

16-Pin SOIC

TIO1/P0.6	1	16	P1.6/SMISO
TIO0/P0.5	2	15	P1.5/SMOSI
INT2/P0.4	3	14	P1.4/SCLK
INT1/P0.3	4	13	P1.3/SSEL
INT0/P0.2	5	12	P1.2
P0.1	6	11	VCC
P0.0	7	10	P1.1/D–
VSS	8	9	P1.0/D+

CY7C63803 16-Pin SOIC

TIO1/P0.6	1	16	P1.6/SMISO
TIO0/P0.5	2	15	P1.5/SMOSI
INT2/P0.4	3	14	P1.4/SCLK
INT1/P0.3	4	13	P1.3/SSEL
INT0/P0.2	5	12	P1.2/VREG
P0.1	6	11	VCC
P0.0	7	10	P1.1/D–
VSS	8	9	P1.0/D+

	CY7C63813					CY7C63813
	18-Pin PDIP				18-Pin SOIC
	SSEL/P1.3	1	18	P1.2/VREG	P0.7	1	18	P1.7
	SCLK/P1.4	2	17	VCC	TIO1/P0.6	2	17	P1.6/SMISO
	SMOSI/P1.5	3	16	P1.1/D–	TIO0/P0.5	3	16	P1.5/SMOSI
	SMISO/P1.6	4	15	P1.0/D+	INT2/P0.4	4	15	P1.4/SCLK
	P1.7	5	14	VSS	INT1/P0.3	5	14	P1.3/SSEL
	P0.7	6	13	P0.0	INT0/P0.2	6	13	P1.2/VREG
	TIO1/P0.6	7	12	P0.1	P0.1	7	12	VCC
			11
	TIO0/P0.5	8		P0.2/INT0	P0.0	8	11	P1.1/D–
	INT2/P0.4	9	10	P0.3/INT1	VSS	9	10	P1.0/D+
		CY7C63823				CY7C63823
	24-Pin QSOP
					24-Pin SOIC

	NC	1	24	P1.7	NC	1	24	NC
	P0.7	2	23	P1.6/SMISO
					P0.7	2	23	P1.7
	TIO1/P0.6	3	22	P1.5/SMOSI
					TIO1/P0.6	3	22	P1.6/SMISO
	TIO0/P0.5	4	21	P1.4/SCLK
					TIO0/P0.5	4	21	P1.5/SMOSI
	INT2/P0.4	5	20	P3.1
					INT2/P0.4	5	20	P1.4/SCLK
	INT1/P0.3	6	19	P3.0
					INT1/P0.3	6	19	P3.1
	INT0/P0.2	7	18	P1.3/SSEL
					INT0/P0.2	7	18	P3.0
	P0.1	8	17	P1.2/VREG
					P0.1	8	17	P1.3/SSEL
	P0.0	9	16	VCC
					P0.0	9	16	P1.2/VREG
	P2.1	10	15	P1.1/D–
					P2.1	10	15	VCC
	P2.0	11	14	P1.0/D+
					P2.0	11	14	P1.1/D–
	NC	12	13	VSS
					VSS	12	13	P1.0/D+

CY7C63833													32-Pin QFN																CY7C63833										32-Pin Sawn QFN
		P0.7			NC			NC			NC			NC			NC			P1.7			P1.6/MISO									P0.7		NC		NC		NC			NC			NC				P1.7			P1.6/MISO


	32				31			30			29			28			27			26			25									32			31		30		29			28			27			26		25
	32				31			30			29			28			27			26			25						P0.6/TIO1		1																			24				P1.5/SMOSI
P0.6/TIO1		1																					24					P1.5/SMOSI

																													P0.5/TIO0																					23				P1.4/SCLK

P0.5/TIO0		2																					23					P1.4/SCLK			2
																															2
																													P0.4/INT2																					22				P3.1

P0.4/INT2		3																					22					P3.1			3
																															3
																													P0.3/INT1																					21				P3.0

P0.3/INT1		4																					21					P3.0			4
																															4
																													P0.2/INT0		5																			20				P1.3/SSEL

P0.2/INT0		5																					20					P1.3/SSEL

																													P0.1		6																			19				NC

P0.1		6																					19					NC

																													P0.0																					18				P1.2/VREG

P0.0		7																					18					P1.2/VREG			7
																															7
																													P2.1																					17				NC

P2.1		8																					17					NC			8
																															8
																															9			10		11		12			13			14			15			16

			9		10			11			12			13			14			15			16

																															P2.0			NC		NC			NC		Vss			P1.0/D+			P1.1/D-				Vdd
		P2.0			NC			NC			NC			Vss			P1.0/D+			P1.1/D-			Vdd								P2.0			NC		NC			NC		Vss			P1.0/D+			P1.1/D-				Vdd

Document 38-08035 Rev. *K

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Contents Features ApplicationsCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08Logic Block Diagram GpioIntroduction ConventionsPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a CPU Architecture No connectSupply GroundCPU Registers Flags RegisterAddressing Modes Source Direct Opcode Operand Source Indexed Opcode Operand10. Destination Direct Opcode Operand Destination Indexed12. Destination Direct Source Immediate Opcode Operand 13. Destination Indexed Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2Memory Organization Flash Program Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2Data Memory Organization FlashSrom Stack begins here and grows upwardSrom Function Descriptions Srom Function Parameters Variable Name Sram AddressSrom Return Codes Description ReadBlock Parameters Name Address DescriptionProtection Modes Settings Description Marketing WriteBlock Parameters Name Address DescriptionEraseBlock Parameters Name Address Description Block Block nProtectBlock Parameters Name Address Description EraseAll Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No BuzzUSB Osclock Clock Configuration Osclckcr 0x39 R/W Timer Clock Config Tmrclkcr 0x31 R/WBit 72 Reserved = TcapclkTimer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/WReset Sleep Mode Power on ResetWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 WSleep Sequence Wake up SequenceLow Power in Sleep Mode Wake Up TimingLow Voltage Detect Control Low Voltage Control Register Lvdcr 0x1E3 R/WBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxVoltage Monitor Comparators Register Vltcmp 0x1E4 R Bit 72 Reserved Bit 1 LVDECO Trim Register ECO Ecotr 0x1EB R/WPort Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/WP0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/WP0.7 Configuration P07CR 0x0C R/W 10. P1.0/D+ Configuration P10CR 0x0D R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W13. P1.3 Configuration P13CR 0x10 R/W 14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/W17. P3 Configuration P3CR 0x16 R/W Serial Peripheral Interface SPISPI Data Register SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Timer Registers Free Running Timer Low order Byte Frtmrl 0x20 R/WFree Running Timer High-order Byte Frtmrh 0x21 R/W RegistersTimer Capture 0 Rising TIO0R 0x22 R/W Timer Capture 1 Rising TIO1R 0x23 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/WProgrammable Interval Timer High Pitmrh 0x27 R Bit 74 ReservedProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/W11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural DescriptionInterrupt Processing Interrupt Trigger ConditionsInterrupt Latency PCH PC158 is cleared to zeroInterrupt Registers Interrupt Clear 0 INTCLR0 0xDA R/WInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/WInterrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/WVreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB Transceiver Configuration USB Transceiver Configure Register Usbxcr 0x74 R/WUSB/PS2 Transceiver USB Serial Interface Engine SIEUSB Device USB Device AddressEndpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Endpoint 1 and 2 Mode Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/WBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/WUSB Mode Tables Mode ColumnEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WDetails of Mode for Differing Traffic Conditions SETUP, IN, and OUT ColumnsCount Fifo Addr Name Default Register SummaryTmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency CharacteristicsDC Characteristics Absolute Maximum RatingsDetect 3V RegulatorAC Characteristics General Purpose IO InterfaceParameter Description Conditions Min Typical Max Unit Clock CpuclkUSB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Gpio Timing Diagram Clock TimingDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package HandlingPackage Diagrams Pin 300-Mil Molded DIP P1Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Added block diagrams and timing diagrams Updated part numbers in the headerRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration detailsVGT/AESA CMCC/PYRSWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.