Cypress CY7C638xx Srom Function Descriptions, Srom Function Parameters Variable Name Sram Address

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CY7C63310, CY7C638xx

Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SROM function begins execution. This would be the Stack Pointer value when the SSC opcode is executed, plus three. If either of the keys do not match the expected values, the M8C halts (with the exception of the SWBootReset function). The following code puts the correct value in KEY1 and KEY2. The code starts with a halt, to force the program to jump directly into the setup code and not run into it.

halt

SSCOP: mov [KEY1], 3ah mov X, SP

mov A, X add A, 3

mov [KEY2], A

Table 9-2. SROM Function Parameters

Variable Name

SRAM Address

Key1/Counter/Return Code

0,F8h

 

 

Key2/TMP

0,F9h

 

 

BlockID

0,FAh

 

 

Pointer

0,FBh

 

 

Clock

0,FCh

 

 

Mode

0,FDh

 

 

Delay

0,FEh

 

 

PCL

0,FFh

 

 

9.4.1 Return Codes

The SROM also features Return Codes and Lockouts.

Return codes aid in the determination of the success or failure of a particular function. The return code is stored in KEY1’s position in the parameter block. The CheckSum and TableRead functions do not have return codes because KEY1’s position in the parameter block is used to return other data.

Table 9-3. SROM Return Codes

Return Code

Description

00h

Success

 

 

01h

Function not allowed due to level of protection

 

on block.

02h

Software reset without hardware reset.

 

 

03h

Fatal error, SROM halted.

 

 

9.5 SROM Function Descriptions

9.5.1 SWBootReset Function

The SROM function, SWBootReset, is the function that is responsible for transitioning the device from a reset state to running user code. The SWBootReset function is executed whenever the SROM is entered with an M8C accumulator value of 00h: the SRAM parameter block is not used as an input to the function. This happens by design after a hardware reset, because the M8C's accumulator is reset to 00h or when the user code executes the SSC instruction with an accumulator value of 00h. The SWBootReset function is not executed when the SSC instruction is executed with a bad key value and a non-zero function code. An enCoRe II device executes the HALT instruction if a bad value is given for either KEY1 or KEY2.

The SWBootReset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the M8C to run user code.

9.5.2 ReadBlock Function

The ReadBlock function is used to read 64 contiguous bytes from Flash: a block.

This function first checks the protection bits and determines if the desired BLOCKID is readable. If the read protection is turned on, the ReadBlock function exits setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h, indicating a read failure. If read protection is not enabled, the function reads 64 bytes from the Flash using a ROMX instruction and stores the results in the SRAM using an MVI instruction. The first of the 64 bytes are stored in the SRAM at the address indicated by the value of the POINTER parameter. When the ReadBlock completes successfully, the accumulator, KEY1, and KEY2 all have a value of 00h.

Table 9-4. ReadBlock Parameters

Name

Address

Description

KEY1

0,F8h

3Ah

 

 

 

KEY2

0,F9h

Stack Pointer value, when SSC is

 

 

executed.

BLOCKID

0,FAh

Flash block number

 

 

 

POINTER

0,FBh

First of 64 addresses in SRAM

 

 

where returned data must be stored.

Read, write, and erase operations may fail if the target block is read or write protected. Block protection levels are set during device programming.

The EraseAll function overwrites data in addition to leaving the entire user Flash in the erase state. The EraseAll function loops through the number of Flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. After all the user space in all the Flash macros are erased, a second loop erases and then programs each protection block with zeros.

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Contents San Jose, CA Document 38-08035 Rev. *K Revised December 08 FeaturesApplications Cypress Semiconductor Corporation 198 Champion CourtGpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Pin Description Gpio Port 1 bit 0/USB D+ 1 If this pin is used as aGpio Port 1 bit 1/USB D- 1 If this pin is used as a Ground CPU ArchitectureNo connect SupplyFlags Register CPU RegistersAddressing Modes Destination Indexed Source Direct Opcode OperandSource Indexed Opcode Operand 10. Destination Direct Opcode Operand15. Source Indirect Post Increment Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 14. Destination Direct Source Direct Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryEP0 EP1 EP2 Memory OrganizationFlash Program Memory Organization POR/LVD INT0Stack begins here and grows upward Data Memory OrganizationFlash SromReadBlock Parameters Name Address Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address Srom Return Codes DescriptionBlock Block n Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description EraseBlock Parameters Name Address Description11. Return values for Table Read Table Number Return Value ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 10. Table Read Parameters Name Address DescriptionSrom Table Clocking Checksum Function12. Checksum Parameters Name Address Description Clock Block Diagram Clock Architecture Description Iosc Trim Iosctr 0x34 R/WBit 40 Gain CPU/USB Clock Config Cpuclkcr 0x30 R/W Lposc Trim Lposctr 0x36 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/W= Tcapclk USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W Bit 72 ReservedInterval Timer Clock Itmrclk Timer Capture Clock TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Reset Watchdog Timer Reswdt 0xE3 W Sleep ModePower on Reset Watchdog Timer ResetWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeBit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10ECO Ecotr 0x1EB R/W Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Trim RegisterGeneral Purpose IO Gpio Ports Port Data RegistersP0 Data Register P0DATA0x00 R/W P1 Data Register P1DATA 0x01 R/W P2 Data Register P2DATA 0x02 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W12. P1.2 Configuration P12CR 0x0F R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 11. P1.1/D- Configuration P11CR 0x0E R/W16. P2 Configuration P2CR 0x15 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 15. P1.7 Configuration P17CR 0x14 R/WSPI Data Register Spidata 0x3C R/W 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data RegisterSPI Configure Register SPI Interface Pins SPI Mode Timing vs. LSB First, Cpol and CphaSclk Ssel DAT a Registers Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W Free Running Timer High-order Byte Frtmrh 0x21 R/WTimer Capture 1 Falling TIO1F 0x25 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Falling TIO0F 0x24 R/W10. Programmable Interval Reload High Pirh 0x29 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved Programmable Interval Reload Low Pirl 0x28 R/WTimer Capture 11. Timer Configuration Tmrcr 0x2A R/WBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerPCH PC158 is cleared to zero Interrupt ProcessingInterrupt Trigger Conditions Interrupt LatencyInterrupt Clear 2 INTCLR2 0xDC R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 1 INTCLR1 0xDB R/WBit 7 Enable Software Interrupt Enswint Interrupt Mask 3 INTMSK3 0xDE R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WRegulator Output Vreg ControlVreg Control Register Vregcr 0x73 R/W USB Serial Interface Engine SIE USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB/PS2 TransceiverUSB Device Address Usbcr 0x40 R/W USB DeviceUSB Device Address Endpoint 0, 1, and 2 CountEndpoint 0 Mode Endpoint 0 Mode EP0MODE 0x44 R/WBit 30 Mode Endpoint 0 Data EP0DATA 0x50-0x57 R/W Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Bit 7 StallEndpoint 2 Data EP2DATA 0x60-0x67 R/W USB Mode TablesMode Column Encoding ColumnSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency Characteristics3V Regulator DC CharacteristicsAbsolute Maximum Ratings DetectCpuclk AC CharacteristicsGeneral Purpose IO Interface Parameter Description Conditions Min Typical Max Unit ClockNon-USB Mode Driver Characteristics USB Data TimingSPI Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed Gpio port 4 configuration details Added block diagrams and timing diagramsUpdated part numbers in the header Removed 638xx die diagram and die form pad assignmentCMCC/PYRS VGT/AESASales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

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In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
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