CY7C63310, CY7C638xx
Table 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Bit # | 7 | 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
Field |
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| Reserved |
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| LVD | PPOR | |
Read/Write | – | – | – |
| – | – | – | R | R |
Default | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 |
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This read only register allows reading the current state of the
Bit [7:2]: Reserved
Bit 1: LVD
This bit is set to indicate that the
0 = No
1= A
This bit is set to indicate that the
0 = No
1 = A
Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
13.0.1 ECO Trim Register
Table 13-3. ECO (ECO_TR) [0x1EB] [R/W]
Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 |
Field | Sleep Duty Cycle [1:0] |
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| Reserved |
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| ||
Read/Write | R/W | R/W | – | – | – |
| – | – | – |
Default | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 |
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This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection circuit.
Bit [7:6]: Sleep Duty Cycle [1:0]
0 0 = 1/128 periods of the Internal 32 kHz
Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
Document | Page 32 of 83 |
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