Cypress CY7C638xx, CY7C63310 manual Tmrcr

Page 65

CY7C63310, CY7C638xx

24. Register Summary (continued)

The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.

Addr

Name

7

6

5

4

3

2

1

0

R/W

Default

2A

TMRCR

First Edge

8-bit capture Prescale

Cap0 16bit

 

Reserved

 

bbbbb---

00000000

 

 

Hold

 

 

 

Enable

 

 

 

 

 

2B

TCAPINTE

 

Reserved

 

Cap1 Fall

Cap1 Rise

Cap0 Fall

Cap0 Rise

----bbbb

00000000

 

 

 

 

 

 

Active

Active

Active

Active

 

 

2C

TCAPINTS

 

Reserved

 

Cap1 Fall

Cap1 Rise

Cap0 Fall

Cap0 Rise

----bbbb

00000000

 

 

 

 

 

 

Active

Active

Active

Active

 

 

30

CPUCLKCR

Reserved

USB

USB CLK

 

Reserved

 

CPU

-bb----b

00010000

 

 

 

CLK/2

Select

 

 

 

 

CLK Select

 

 

 

 

 

Disable

 

 

 

 

 

 

 

 

31

ITMRCLKCR

TCAPCLK Divider

TCAPCLK Select

ITMRCLK Divider

ITMRCLK Select

bbbbbbbb

10001111

 

 

 

 

 

 

 

 

 

 

 

 

32

CLKIOCR

 

Reserved

 

 

Reserved

 

CLKOUT Select

---bbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

34

IOSCTR

 

foffset[2:0]

 

 

 

Gain[4:0]

 

 

bbbbbbbb

000ddddd

 

 

 

 

 

 

 

 

 

 

 

 

36

LPOSCTR

32 kHz

Reserved

32 kHz Bias Trim [1:0]

 

32 kHz Freq Trim [3:0]

 

b-bbbbbb

dddddddd

 

 

Low

 

 

 

 

 

 

 

 

 

 

 

Power

 

 

 

 

 

 

 

 

 

39

OSCLCKCR

 

 

Reserved

 

 

Fine Tune

USB

------bb

00000000

 

 

 

 

 

 

 

 

Only

Osclock

 

 

 

 

 

 

 

 

 

 

 

Disable

 

 

3C

SPIDATA

 

 

 

SPIData[7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

3D

SPICR

Swap

LSB First

Comm Mode

CPOL

CPHA

SCLK Select

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

40

USBCR

USB

 

 

Device Address[6:0]

 

 

bbbbbbbb

00000000

 

 

Enable

 

 

 

 

 

 

 

 

 

41

EP0CNT

Data

Data Valid

Reserved

 

Byte Count[3:0]

 

bbbbbbbb

00000000

 

 

Toggle

 

 

 

 

 

 

 

 

 

42

EP1CNT

Data

Data Valid

Reserved

 

Byte Count[3:0]

 

bbbbbbbb

00000000

 

 

Toggle

 

 

 

 

 

 

 

 

 

43

EP2CNT

Data

Data Valid

Reserved

 

Byte Count[3:0]

 

bbbbbbbb

00000000

 

 

Toggle

 

 

 

 

 

 

 

 

 

44

EP0MODE

Setup

IN rcv’d

OUT rcv’d

ACK’d trans

 

Mode[3:0]

 

ccccbbbb

00000000

 

 

rcv’d

 

 

 

 

 

 

 

 

 

45

EP1MODE

Stall

Reserved

NAK Int

Ack’d trans

 

Mode[3:0]

 

b-bcbbbb

00000000

 

 

 

 

Enable

 

 

 

 

 

 

 

46

EP2MODE

Stall

Reserved

NAK Int

Ack’d trans

 

Mode[3:0]

 

b-bcbbbb

00000000

 

 

 

 

Enable

 

 

 

 

 

 

 

50–57

EP0DATA

 

 

 

Endpoint 0 Data Buffer [7:0]

 

 

bbbbbbbb

????????

 

 

 

 

 

 

 

 

 

 

58–5F

EP1DATA

 

 

 

Endpoint 1 Data Buffer [7:0]

 

 

bbbbbbbb

????????

 

 

 

 

 

 

 

 

 

 

60–67

EP2DATA

 

 

 

Endpoint 2 Data Buffer [7:0]

 

 

bbbbbbbb

????????

 

 

 

 

 

 

 

 

 

 

 

73

VREGCR

 

 

Reserved

 

 

Keep Alive

VREG

------bb

00000000

 

 

 

 

 

 

 

 

 

Enable

 

 

74

USBXCR

USB Pull

 

 

Reserved

 

 

USB Force

b------b

00000000

 

 

up Enable

 

 

 

 

 

 

State

 

 

DA

INT_CLR0

GPIO Port

Sleep

INT1

GPIO Port

SPI

SPI Transmit

INT0

POR/LVD

bbbbbbbb

00000000

 

 

1

Timer

 

0

Receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DB

INT_CLR1

TCAP0

Prog

1-ms

USB Active

USB Reset

USB EP2

USB EP1

USB EP0

bbbbbbbb

00000000

 

 

 

Interval

Timer

 

 

 

 

 

 

 

 

 

 

Timer

 

 

 

 

 

 

 

 

DC

INT_CLR2

Reserved

Reserved

GPIO Port

GPIO Port 2

PS/2 Data

INT2

16-bit

TCAP1

-bbbbbbb

00000000

 

 

 

 

3

 

Low

 

Counter

 

 

 

 

 

 

 

 

 

 

 

Wrap

 

 

 

DE

INT_MSK3

ENSWINT

 

 

 

Reserved

 

 

 

b-------

00000000

 

 

 

 

 

 

 

 

 

 

 

 

DF

INT_MSK2

Reserved

Reserved

GPIO Port

GPIO Port 2

PS/2 Data

INT2

16-bit

TCAP1

-bbbbbbb

00000000

 

 

 

 

3

Int Enable

Low Int

Int Enable

Counter

Int Enable

 

 

 

 

 

 

Int Enable

 

Enable

 

Wrap

 

 

 

 

 

 

 

 

 

 

 

Int Enable

 

 

 

E1

INT_MSK1

TCAP0

Prog

1-ms

USB Active

USB Reset

USB EP2

USB EP1

USB EP0

bbbbbbbb

00000000

 

 

Int Enable

Interval

Timer

Int Enable

Int Enable

Int Enable

Int Enable

Int Enable

 

 

 

 

 

Timer

Int Enable

 

 

 

 

 

 

 

 

 

 

Int Enable

 

 

 

 

 

 

 

 

E0

INT_MSK0

GPIO Port

Sleep

INT1

GPIO Port 0

SPI

SPI Transmit

INT0

POR/LVD

bbbbbbbb

00000000

 

 

1

Timer

Int Enable

Int Enable

Receive

Int Enable

Int Enable

Int Enable

 

 

 

 

Int Enable

Int Enable

 

 

Int Enable

 

 

 

 

 

Document 38-08035 Rev. *K

Page 65 of 83

[+] Feedback

Page 64 Page 66
Image 65
Page 64 Page 66
Contents Applications FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08Gpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 1/USB D- 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 0/USB D+ 1 If this pin is used as a No connect CPU ArchitectureSupply GroundFlags Register CPU RegistersAddressing Modes Source Indexed Opcode Operand Source Direct Opcode Operand10. Destination Direct Opcode Operand Destination Indexed13. Destination Indexed Source Immediate Opcode Operand 12. Destination Direct Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryFlash Program Memory Organization Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2Flash Data Memory OrganizationSrom Stack begins here and grows upwardSrom Function Parameters Variable Name Sram Address Srom Function DescriptionsSrom Return Codes Description ReadBlock Parameters Name Address DescriptionWriteBlock Parameters Name Address Description Protection Modes Settings Description MarketingEraseBlock Parameters Name Address Description Block Block nEraseAll Parameters Name Address Description ProtectBlock Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table 12. Checksum Parameters Name Address Description ClockingChecksum Function Clock Block Diagram Bit 40 Gain Clock Architecture DescriptionIosc Trim Iosctr 0x34 R/W Bit 41 Reserved CPU/USB Clock Config Cpuclkcr 0x30 R/WLposc Trim Lposctr 0x36 R/W Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/WTimer Clock Config Tmrclkcr 0x31 R/W USB Osclock Clock Configuration Osclckcr 0x39 R/WBit 72 Reserved = TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Interval Timer Clock ItmrclkTimer Capture Clock Tcapclk Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Power on Reset Sleep ModeWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 WWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeLow Voltage Control Register Lvdcr 0x1E3 R/W Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxBit 72 Reserved Bit 1 LVD Voltage Monitor Comparators Register Vltcmp 0x1E4 RECO Trim Register ECO Ecotr 0x1EB R/WP0 Data Register P0DATA0x00 R/W General Purpose IO Gpio PortsPort Data Registers P3 Data Register P3DATA 0x03 R/W P1 Data Register P1DATA 0x01 R/WP2 Data Register P2DATA 0x02 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W10. P1.0/D+ Configuration P10CR 0x0D R/W P0.7 Configuration P07CR 0x0C R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 13. P1.3 Configuration P13CR 0x10 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/WSerial Peripheral Interface SPI 17. P3 Configuration P3CR 0x16 R/WSPI Data Register SPI Data Register Spidata 0x3C R/WSPI Configure Register Sclk Ssel DAT a SPI Interface PinsSPI Mode Timing vs. LSB First, Cpol and Cpha Free Running Timer Low order Byte Frtmrl 0x20 R/W Timer RegistersFree Running Timer High-order Byte Frtmrh 0x21 R/W RegistersTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/WBit 74 Reserved Programmable Interval Timer High Pitmrh 0x27 RProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/WBit 20 Reserved Timer Capture11. Timer Configuration Tmrcr 0x2A R/W 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerInterrupt Trigger Conditions Interrupt ProcessingInterrupt Latency PCH PC158 is cleared to zeroInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt RegistersInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Bit 7 Enable Software Interrupt EnswintInterrupt Mask 3 INTMSK3 0xDE R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WVreg Control Register Vregcr 0x73 R/W Regulator OutputVreg Control USB Transceiver Configure Register Usbxcr 0x74 R/W USB Transceiver ConfigurationUSB/PS2 Transceiver USB Serial Interface Engine SIEUSB Device Address USB DeviceEndpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/WBit 30 Mode Endpoint 0 ModeEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 1 and 2 ModeBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/WMode Column USB Mode TablesEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency CharacteristicsAbsolute Maximum Ratings DC CharacteristicsDetect 3V RegulatorGeneral Purpose IO Interface AC CharacteristicsParameter Description Conditions Min Typical Max Unit Clock CpuclkSPI Timing Non-USB Mode Driver CharacteristicsUSB Data Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Updated part numbers in the header Added block diagrams and timing diagramsRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration detailsCMCC/PYRS VGT/AESAUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.
Top Page Image Contents