Cypress CY7C638xx, CY7C63310 manual USB Mode Tables, Mode Column, Encoding Column

Page 61

CY7C63310, CY7C638xx

Table 21-7. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

 

 

 

Endpoint 2 Data Buffer [7:0]

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

Unknown

Unknown

Unknown

Unknown

Unknown

Unknown

Unknown

Unknown

 

 

 

 

 

 

 

 

 

The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67.

The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values of the Endpoint Data Registers are unknown.

Unlike past enCoRe parts the USB data buffers are only accessible in the IO space of the processor.

22. USB Mode Tables

Mode

Encoding

SETUP

IN

OUT

Comments

DISABLE

0000

Ignore

Ignore

Ignore

Ignore all USB traffic to this endpoint. Used by Data and

 

 

 

 

 

Control endpoints.

NAK IN/OUT

0001

Accept

NAK

NAK

NAK IN and OUT token. Control endpoint only.

 

 

 

 

 

 

STATUS OUT ONLY

0010

Accept

STALL

Check

STALL IN and ACK zero byte OUT. Control endpoint

 

 

 

 

 

only.

STALL IN/OUT

0011

Accept

STALL

STALL

STALL IN and OUT token. Control endpoint only.

 

 

 

 

 

 

STATUS IN ONLY

0110

Accept

TX0 byte

STALL

STALL OUT and send zero byte data for IN token. Con-

 

 

 

 

 

trol endpoint only.

ACK OUT – STATUS

1011

Accept

TX0 byte

ACK

ACK the OUT token or send zero byte data for IN token.

IN

 

 

 

 

Control endpoint only.

ACK IN – STATUS

1111

Accept

TX Count

Check

Respond to IN data or Status OUT. Control endpoint

OUT

 

 

 

 

only.

 

 

 

 

 

 

NAK OUT

1000

Ignore

Ignore

NAK

Send NAK handshake to OUT token. Data endpoint

 

 

 

 

 

only.

ACK OUT (STALL = 0)

1001

Ignore

Ignore

ACK

This mode is changed by the SIE to mode 1000 on is-

 

 

 

 

 

suance of ACK handshake to an OUT. Data endpoint

 

 

 

 

 

only.

ACK OUT (STALL = 1)

1001

Ignore

Ignore

STALL

STALL the OUT transfer.

 

 

 

 

 

 

NAK IN

1100

Ignore

NAK

Ignore

Send NAK handshake for IN token. Data endpoint only.

 

 

 

 

 

 

ACK IN (STALL = 0)

1101

Ignore

TX Count

Ignore

This mode is changed by the SIE to mode 1100 after

 

 

 

 

 

receiving ACK handshake to an IN data. Data endpoint

 

 

 

 

 

only.

ACK IN (STALL = 1)

1101

Ignore

STALL

Ignore

STALL the IN transfer. Data endpoint only.

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

0101

Ignore

Ignore

Ignore

These modes are not supported by SIE. Firmware must

 

 

 

 

 

not use this mode in Control and Data endpoints.

Reserved

0111

Ignore

Ignore

Ignore

 

 

 

 

 

 

 

Reserved

1010

Ignore

Ignore

Ignore

 

 

 

 

 

 

 

Reserved

0100

Ignore

Ignore

Ignore

 

 

 

 

 

 

 

Reserved

1110

Ignore

Ignore

Ignore

 

 

 

 

 

 

 

22.1 Mode Column

The 'Mode' column contains the mnemonic names given to the modes of the endpoint. The mode of the endpoint is determined by the 4-bit binaries in the 'Encoding' column as discussed in the following sections. The Status IN and Status OUT represent the status IN or OUT stage of the control transfer.

22.2 Encoding Column

The contents of the 'Encoding' column represent the Mode Bits [3:0] of the Endpoint Mode Registers (Table 21-3on page 59 and Table 21-4on page 60). The endpoint modes determine how the SIE responds to different tokens that the host sends to the endpoints. For example, if the Mode Bits [3:0] of the Endpoint 0 Mode Register are set to '0001', which is NAK IN/OUT mode, the SIE sends an ACK handshake in response to SETUP tokens and NAK any IN or OUT tokens.

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Contents Applications FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08Gpio Logic Block DiagramConventions IntroductionPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a No connect CPU ArchitectureSupply GroundFlags Register CPU RegistersAddressing Modes Source Indexed Opcode Operand Source Direct Opcode Operand10. Destination Direct Opcode Operand Destination Indexed13. Destination Indexed Source Immediate Opcode Operand 12. Destination Direct Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set SummaryFlash Program Memory Organization Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2Flash Data Memory OrganizationSrom Stack begins here and grows upwardSrom Function Parameters Variable Name Sram Address Srom Function DescriptionsSrom Return Codes Description ReadBlock Parameters Name Address DescriptionWriteBlock Parameters Name Address Description Protection Modes Settings Description MarketingEraseBlock Parameters Name Address Description Block Block nEraseAll Parameters Name Address Description ProtectBlock Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/WTimer Clock Config Tmrclkcr 0x31 R/W USB Osclock Clock Configuration Osclckcr 0x39 R/WBit 72 Reserved = TcapclkTimer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep ModeReset Power on Reset Sleep ModeWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 WWake up Sequence Sleep SequenceWake Up Timing Low Power in Sleep ModeLow Voltage Control Register Lvdcr 0x1E3 R/W Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxBit 72 Reserved Bit 1 LVD Voltage Monitor Comparators Register Vltcmp 0x1E4 RECO Trim Register ECO Ecotr 0x1EB R/WPort Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/WP0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W10. P1.0/D+ Configuration P10CR 0x0D R/W P0.7 Configuration P07CR 0x0C R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 13. P1.3 Configuration P13CR 0x10 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/WSerial Peripheral Interface SPI 17. P3 Configuration P3CR 0x16 R/WSPI Data Register SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Free Running Timer Low order Byte Frtmrl 0x20 R/W Timer RegistersFree Running Timer High-order Byte Frtmrh 0x21 R/W RegistersTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/WBit 74 Reserved Programmable Interval Timer High Pitmrh 0x27 RProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/W11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt ControllerInterrupt Trigger Conditions Interrupt ProcessingInterrupt Latency PCH PC158 is cleared to zeroInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt RegistersInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/WInterrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/WVreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB Transceiver Configure Register Usbxcr 0x74 R/W USB Transceiver ConfigurationUSB/PS2 Transceiver USB Serial Interface Engine SIE USB Device Address USB Device Endpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 1 and 2 ModeBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/WMode Column USB Mode TablesEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WSETUP, IN, and OUT Columns Details of Mode for Differing Traffic ConditionsCount Fifo Register Summary Addr Name DefaultTmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency CharacteristicsAbsolute Maximum Ratings DC CharacteristicsDetect 3V RegulatorGeneral Purpose IO Interface AC CharacteristicsParameter Description Conditions Min Typical Max Unit Clock CpuclkUSB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Clock Timing Gpio Timing DiagramDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering InformationPin 300-Mil Molded DIP P1 Package DiagramsPin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Updated part numbers in the header Added block diagrams and timing diagramsRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration detailsCMCC/PYRS VGT/AESAWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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