Spectrum Brands MC.31XX manual Pin assignment of the multipin connector, Option Digital inputs

Page 101

Pin assignment of the multipin connector

Pin assignment of the multipin connector

The 40 lead multipin connector is used for different options, like “Extra I/O“ or the additional digital inputs (on analog acquisition boards only) or additional digital outputs (on analog generation boards only).

The connectors mentioned here are mounted on an extra bracket.

The pin assignment depends on which of the below mentioned options are installed.

Extra I/O with external connector(Option -XMF)

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

D0

GND

D1

GND

D2

GND

D3

GND

D4

GND

D5

GND

D6

GND

D7

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

D8

GND

D9

GND

D10

GND

D11

GND

D12

GND

D13

GND

D14

GND

D15

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

D16

GND

D17

GND

D18

GND

D19

GND

D20

GND

D21

GND

D22

GND

D23

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A0

GND

GND

GND

A1

GND

GND

GND

A2

GND

GND

GND

A3

GND

GND

GND

n.c.

n.c.

n.c.

n.c.

A3…A0 are the pins for the analog outputs, while D23…D0 are the 24 digital I/Os.

Option “Digital inputs“

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

D8

GND

D9

GND

D10

GND

D11

GND

D12

GND

D13

GND

D14

GND

D15

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

D0

GND

D1

GND

D2

GND

D3

GND

D4

GND

D5

GND

D6

GND

D7

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

D24

GND

D25

GND

D26

GND

D27

GND

D28

GND

D29

GND

D30

GND

D31

GND

n.c.

n.c.

n.c.

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

D16

GND

D17

GND

D18

GND

D19

GND

D20

GND

D21

GND

D22

GND

D23

GND

n.c.

n.c.

n.c.

n.c.

Depending on the type of board the digital inputs are found on the upper four bits of the following analog channels:

Type

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

MC.31x0

D0…D3

D4…D7

n.u.

n.u.

n.u.

n.u.

n.u.

n.u.

MC.31x1

D0…D3

D4…D7

D8…D11

D12…D15

n.u.

n.u.

n.u.

n.u.

MC.31x2

D0…D3

D4…D7

D8…D11

D12…D15

D16…D19

D20…D23

D24…D27

D28…D31

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Inputs Standard acquisition modesOption Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/OPreface IntroductionGeneral Information PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional optionsTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersIntroductionHardware information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Software Driver Installation Windows InstallationWindows Version controlDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Overview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench Software OverviewHeader files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ BuilderNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsType definition Delphi Pascal Programming InterfaceInclude Driver ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterInstalled features and options Installed memoryHardware version Date of productionUsed type of driver Used interrupt lineProgramming the Board Initialization Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog InputsImportant note on channels selection Analog InputsRerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjsave ADJUSER0 Spcadjautoadj AdjallProgramming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerCommand register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organizationReading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming General Information Fifo ModeBackground Fifo Read Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsFifo acquisition example Example Fifo acquisition modeSpcfifostart SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generationDirect external clock External clockingMinimum external sample rate Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 General Description Trigger modes and appendant registersSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthOverview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel TmchxoffSpctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffSPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsWhen using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modesTrigger modesOption Multiple Recording Resulting start delaysSpcmemsize SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateAlignement samples per channel End of gate alignementAllowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge triggerExample program Option Gated Sampling Example programChannel trigger Spctriggermode TmttlposOption Timestamp StartReset modeTimestamp modes LimitsFunctions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Digital I/Os Option Extra I/OAnalog Outputs Channel directionProgramming example Option Extra I/O Programming exampleOption Digital inputs Bit Standard Mode Digital Inputs enabledSample format SpcreaddigitalDifferent synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards onlyDefine the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or triggerExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo SpcsyncslavefifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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