Spectrum Brands MC.31XX manual Number of samples on gate signal, Allowed trigger modes

Page 81

Option Gated SamplingTrigger modes

Resulting start delays

Sample rate

Activated channels

 

 

 

external TTL trigger

internal trigger

ext. TTL trigger with

internal trigger with

 

0

1

2

3

4

5

6

7

 

 

activated

activated

 

 

 

synchronization

synchronization

 

 

 

 

 

 

 

 

 

 

 

< 5 MS/s

x

 

 

 

 

 

 

 

-4 samples

+4 samples

-3 samples

+5 samples

> 5 MS/s

x

 

 

 

 

 

 

 

+4 samples

+16 samples

+5 samples

+17 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

< 5 MS/s

x

 

 

 

x

 

 

 

-4 samples

+4 samples

-3 samples

+5 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

> 5 MS/s

x

 

 

 

x

 

 

 

+4 samples

+16 samples

+5 samples

+17 samples

< 2.5 MS/s

x

x

 

 

 

 

 

 

-4 samples

+4 samples

-3 samples

+5 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

> 2.5 MS/s

x

x

 

 

 

 

 

 

+2 samples

+10 samples

+3 samples

+11 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

< 2.5 MS/s

x

x

 

 

x

x

 

 

-4 samples

+4 samples

-3 samples

+5 samples

> 2.5 MS/s

x

x

 

 

x

x

 

 

+2 samples

+10 samples

+3 samples

+11 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

< 1.25 MS/s

x

x

x

x

 

 

 

 

-4 samples

+5 samples

-4 samples

+5 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

> 1.25 MS/s

x

x

x

x

 

 

 

 

-1 samples

+8 samples

-1 samples

+9 samples

< 1.25 MS/s

x

x

x

x

x

x

x

x

-4 samples

+5 samples

-4 samples

+5 samples

 

 

 

 

 

 

 

 

 

 

 

 

 

> 1.25 MS/s

x

x

x

x

x

x

x

x

-1 samples

+8 samples

-1 samples

+9 samples

Number of samples on gate signal

As described above there’s a delay at the start of the gate interval due to the internal memory structure. However this delay can be partly compensated by internal pipelines resulting in a data delay that even can be negative showing the trigger event (acquisition mode only). This data delay is listed in an extra table. But beneath this compensation there’s still the start delay that as a result causes the card to use less samples than the gate signal length. Please refer to the following table to see how many samples less than the length of gate signal are used

Module 0

 

 

Module 1

 

 

 

 

 

 

 

0

1

2

3

0

1

2

3

Mode

Sampling clock

less samples

Sampling clock

less samples

X

 

 

 

 

 

 

 

Standard/FIFO

< 5 MS/s

7

> 5 MS/s

12

X

 

 

 

X

 

 

 

Standard

< 5 MS/s

7

> 5 MS/s

12

X

 

 

 

X

 

 

 

FIFO

< 2.5 MS/s

3

> 2.5 MS/s

6

X

X

 

 

 

 

 

 

Standard/FIFO

< 2.5 MS/s

3

> 2.5 MS/s

6

X

X

 

 

X

X

 

 

Standard

< 2.5 MS/s

3

> 2.5 MS/s

6

X

X

 

 

X

X

 

 

FIFO

< 1.25 MS/s

2

> 1.25 MS/s

3

X

X

X

X

 

 

 

 

Standard/FIFO

< 1.25 MS/s

2

> 1.25 MS/s

3

X

X

X

X

X

X

X

X

Standard

< 1.25 MS/s

2

> 1,25 MS/s

3

X

X

X

X

X

X

X

X

FIFO

< 625 kS/s

1

> 625 kS/s

2

Allowed trigger modes

As mentioned above not all of the possible trigger modes can be used as a gate condition. The following table is showing the allowed trigger modes that can be used and explains the event that has to be detected for gate-start end for gate-end.

External TTL edge trigger

The following table shows the allowed trigger modes when using the external TTL trigger connector:

Mode

Gate start will be detected on

Gate end will be detected on

TM_TTLPOS

positive edge on external trigger

negative edge on external trigger

TM_TTL_NEG

negative edge on external trigger

positive edge on external trigger

External TTL pulsewidth trigger

The following table shows the allowed pulsewidth trigger modes when using the external TTL trigger connector:

Mode

Gate start will be detected on

Gate end will be detected on

TM_TTLHIGH_LP

high pulse of external trigger longer than programmed pulsewidth

negative edge on external trigger

TM_TTLLOW_LP

low pulse of external trigger longer than programmed pulsewidth

positive edge on external trigger

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Inputs Standard acquisition modesOption Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/OPreface IntroductionGeneral Information PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional optionsTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersIntroductionHardware information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Software Driver Installation Windows InstallationWindows Version controlDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Overview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench Software OverviewHeader files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ BuilderNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsType definition Delphi Pascal Programming InterfaceInclude Driver ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterInstalled features and options Installed memoryHardware version Date of productionUsed type of driver Used interrupt lineProgramming the Board Initialization Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog InputsImportant note on channels selection Analog InputsRerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallProgramming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerCommand register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organizationReading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming General Information Fifo ModeBackground Fifo Read Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsFifo acquisition example Example Fifo acquisition modeSpcfifostart SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generationDirect external clock External clockingMinimum external sample rate Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo General Description Trigger modes and appendant registersSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthOverview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel TmchxoffSpctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffSPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsWhen using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modesTrigger modesOption Multiple Recording Resulting start delaysSpcmemsize SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateAlignement samples per channel End of gate alignementAllowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge triggerExample program Option Gated Sampling Example programChannel trigger Spctriggermode TmttlposOption Timestamp StartReset modeTimestamp modes LimitsFunctions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Digital I/Os Option Extra I/OAnalog Outputs Channel directionProgramming example Option Extra I/O Programming exampleOption Digital inputs Bit Standard Mode Digital Inputs enabledSample format SpcreaddigitalDifferent synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards onlyDefine the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or triggerExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo SpcsyncslavefifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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