Spectrum Brands MC.31XX Hardware version, Date of production, Serial number, Installed memory

Page 38

Initialization

Programming the Board

 

 

Hardware version

Since all of the MI, MC and MX boards from Spectrum are modular boards, they consist of one base board and one or two (only PCI and CompactPCI) piggy-back modules. This register SPC_PCIVERSION gives information about the revision of either the base board and the mod- ules. Normally you do not need this information but if you have a support question, please provide the revision together with it.

Register

Value

Direction

Description

SPC_PCIVERSION

2010

r

Board revision: bit 15..8 show revision of the base card, bit 7..0 the revision of the modules

If your board has a piggy-back expansion module mounted (MC und MI series boards only) you can get the hardwareversion with the fol- lowing register.

Register

Value

Direction

Description

SPC_PCIEXTVERSION

2011

r

Board’s expansion module hardware revision as integer value.

Date of production

This register informs you about the production date, which is returned as one 32 bit longword. The upper word is holding the information about the year, while the lower byte informs about the month. The second byte (counting from below) is not used. If you only need to know the production year of your board you have to mask the value accordingly. Normally you do not need this information, but if you have a support question, please provide the revision within.

Register

Value

Direction

Description

SPC_PCIDATE

2020

r

Production date: year in bit 31..16, month in bit 7..0, bit 15..8 are not used

Serial number

This register holds the information about the serial number of the board. This numer is unique and should always be sent together with a support question. Normally you use this information together with the register SPC_PCITYP to verify that multiple measurements are done with the exact same board.

Register

Value

Direction

Description

SPC_PCISERIALNO

2030

r

Serial number of the board

Maximum possible sample rate

This register gives you the maximum possible samplerate the board can run however. The information provided here does not consider any restrictions in the maximum speed caused by special channel settings. For detailed information about the correlation between the maximum samplerate and the number of activated chanels please refer th the according chapter.

Register

Value

Direction

Description

SPC_PCISAMPLERATE

2100

r

Maximum samplerate in Hz as a 32 bit integer value

Installed memory

This register returns the size of the installed on-board memory in bytes as a 32 bit integer value. If you want to know the ammount of samples you can store, you must regard the size of one sample of your Spectrum board. All 8 bit boards can store only sample per byte, while all other boards with 12, 14 and 16 bit use two bytes to store one sample.

Register

Value

Direction

Description

SPC_PCIMEMSIZE

2110

r

Instaleld memory in bytes as a 32 bit integer value

The following example is written for a „two bytes“ per sample board (12, 14 or 16 bit board).

SpcGetParam (hDrv, SPC_PCIMEMSIZE, &lInstMemsize);

printf ("Memory on board: %ld MBytes (%ld MSamples)\n", lInstMemsize /1024 / 1024, lInstMemsize /1024 / 1024 /2);

Installed features and options

The SPC_PCIFEATURES register informs you about the options, that are installed on the board. If you want to know about one option being installed or not, you need to read out the 32 bit value and mask the interesting bit.

Register

Value

Direction

Description

SPC_PCIFEATURES

2120

r

PCI feature register. Holds the installed features and options as a bitfield, so the return value must be

 

 

 

 

masked with one of the masks below to get information about one certain feature.

 

PCIBIT_MULTI

1

Is set if the Option Multiple Recording / Multiple Replay is installed.

 

PCIBIT_DIGITAL

2

Is set if the Option Digital Inputs / Digital Outputs is installed.

 

 

 

 

 

PCIBIT_GATE

32

Is set if the Option Gated Sampling / Gated Replay is installed.

 

PCIBIT_SYNC

512

Is set if the Option Synchronization is installed for that certain board, regardless what kind of synchronization you

 

 

 

use. Boards without this option cannot be synchronized with other boards.

 

PCIBIT_TIMESTAMP

1024

Is set if the Option Timestamp is installed.

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MC.31xx Manual

Page 37 Page 39
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Page 37 Page 39
Contents MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Inputs Fifo ModeProgramming the Board Standard acquisition modesOption Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/OGeneral Information IntroductionPreface PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationIntroductionHardware information Dynamic ParametersOrder information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Linux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview Software OverviewMicrosoft Visual C++ ++ Driver InterfaceHeader files Borland C++ BuilderDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsInclude Driver Delphi Pascal Programming InterfaceType definition ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterHardware version Installed memoryInstalled features and options Date of productionProgramming the Board Initialization Used interrupt lineUsed type of driver Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog InputsChannel Selection Analog InputsSPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjautoadj Adjall Spcadjsave ADJUSER0Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttriggerMaximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organizationValue ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer valueProgramming Background Fifo Read Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo acquisition modeFifo acquisition example SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generationMinimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Trigger modes and appendant registersGeneral Description External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerTTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulsesSpctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses SpcpulsewidthSpctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers TmchxoffSPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 TmchxoffSPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsOption Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modesSpcmemsize Resulting start delaysTrigger modesOption Multiple Recording SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelOption Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge triggerChannel trigger Example programExample program Option Gated Sampling Spctriggermode TmttlposTimestamp modes StartReset modeOption Timestamp LimitsTimestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Analog Outputs Option Extra I/ODigital I/Os Channel directionProgramming example Programming example Option Extra I/OSample format Bit Standard Mode Digital Inputs enabledOption Digital inputs SpcreaddigitalSynchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubLet the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or triggerDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized runSpcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesError Codes AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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