Spectrum Brands MC.31XX Option Multiple Recording, Recording modes, Trigger modes, Standard Mode

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Option Multiple Recording

Recording modes

 

 

Option Multiple Recording

The option Multiple Recording allows the acquisition of data blocks with multiple trigger events without restarting the hardware. The on-board memory will be divided into several segments of the same size. Each segment will be filled with data when a trigger event occures. As this mode is totally done in hardware there is a very small rearm time from end of the acquisition of one segment until the trigger detection is enabled again. You’ll find that rearm time in the technical data section of this manual.

Recording modes

Standard Mode

With every detected trigger event one data block is filled with data. The length of one multiple recording segment is set by the value of the posttrigger register. The total amount of samples to be recorded is defined by the memsize regis- ter.

In most cases memsize will be set to a a multiple of the seg- ment size (postcounter). The table below shows the register for enabling Multiple Recording. For detailed information on how to setup and start the standard acquisition mode please refer to the according chapter eralier in this manual.

When using Multiple Recording pretrigger is not available.

Register

Value

Direction

Description

SPC_MULTI

220000

r/w

Enables Multiple Recording mode.

 

 

 

 

SPC_MEMSIZE

10000

r/w

Defines the total amount of samples to record.

SPC_POSTTRIGGER

10100

r/w

Defines the size of one Multiple Recording segment.

FIFO Mode

The Multiple Recording in FIFO Mode is similar to the Mul- tiple Recording in Standard Mode. The segment size is also set by the postcounter register.

In contrast to the Standard mode you cannot programm a certain total amount of samples to be recorded. The acqui- sition is running until the user stops it. The data is read FIFO block by FIFO block by the driver. These blocks are online available for further data processing by the user program. This mode sigficantly reduces the average data transfer

rate on the PCI bus. This enables you to use faster sample rates then you would be able to in FIFO mode without Multiple Recording. Usually the FIFO blocks are multiples of the Multiple Recording segments.

The advantage of Multiple Recording in FIFO mode is that you can stream data online to the hostsystem. You can make realtime data process- ing or store a huge amount of data to the hard disk. The table below shows the dedicated register for enabling Multiple Recording. For de- tailed information how to setup and start the board in FIFO mode please refer to the according chapter earlier in this manual.

Register

Value

Direction

Description

SPC_MULTI

220000

r/w

Enables Multiple Recording mode.

SPC_POSTTRIGGER

10100

r/w

Defines the size of one Multiple Recording segment.

Trigger modes

In Multiple Recording modes all of the board’s trigger modes are available except the software trigger. Depend- ing on the different trigger modes, the chosen sample rate the used channels and activated board synchronisation (see according chapter for details about synchronizing multiple boards) there are different delay times between the trigger event and the first sampled data (see figure). This delay is necessary as the board is equipped with dy- namic RAM, which needs refresh cycles to keep the data in memory when the board is not recording.

The delay is fix for a certain board setup. All possible de- lays in samples between the trigger event and the first re- corded sample are listed in the table below. A negative amount of samples indicates that the trigger will be visible.

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Inputs Standard acquisition modesOption Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/OPreface IntroductionGeneral Information PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional optionsTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersIntroductionHardware information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Software Driver Installation Windows InstallationWindows Version controlDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Overview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench Software OverviewHeader files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ BuilderNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsType definition Delphi Pascal Programming InterfaceInclude Driver ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterInstalled features and options Installed memoryHardware version Date of productionUsed type of driver Used interrupt lineProgramming the Board Initialization Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog InputsImportant note on channels selection Analog InputsRerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjsave ADJUSER0 Spcadjautoadj AdjallProgramming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerCommand register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organizationReading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming General Information Fifo ModeBackground Fifo Read Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsFifo acquisition example Example Fifo acquisition modeSpcfifostart SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generationDirect external clock External clockingMinimum external sample rate Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 General Description Trigger modes and appendant registersSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthOverview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel TmchxoffSpctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffSPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsWhen using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modesTrigger modesOption Multiple Recording Resulting start delaysSpcmemsize SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateAlignement samples per channel End of gate alignementAllowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge triggerExample program Option Gated Sampling Example programChannel trigger Spctriggermode TmttlposOption Timestamp StartReset modeTimestamp modes LimitsFunctions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Digital I/Os Option Extra I/OAnalog Outputs Channel directionProgramming example Option Extra I/O Programming exampleOption Digital inputs Bit Standard Mode Digital Inputs enabledSample format SpcreaddigitalDifferent synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards onlyDefine the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or triggerExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo SpcsyncslavefifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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