Spectrum Brands MC.31XX manual Trigger modes and appendant registers, General Description

Page 62

General Description

Trigger modes and appendant registers

 

 

Trigger modes and appendant registers

General Description

The trigger modes of the Spectrum MI, MC and MX A/D boards are very complex and give you the possibility to detect nearly any trigger event, you can think of.

You can choose between seven external TTL trigger modes and up to 18 internal trigger modes including software and channel trigger, de- pending on your type of board. Five of the internal trigger modes can be independently set set for each input channel (on A/D boards only) resulting in a even bigger variety of modes. This chapter is about to explain all of the different trigger modes and setting up the board’s registers for the desired mode.

Every analog Spectrum board has one dedicated SMB connector mounted in it’s bracket for feeding in an external trigger signal or outputting a trigger signal of an internal trigger event. Due to the fact that only one connector is available for external trigger I/O, it is not possible to forward the fed in external trigger signal to another board. If this is however necessary, you need to split up the external trigger signal before.

Software trigger

The software trigger is the easiest way of triggering any Spectrum board. The acquisition or replay of data will start immediately af- ter starting the board. The only delay results from the time the board needs for its setup.

Register

Value

Direction

Description

SPC_TRIGGERMODE

40000

r/w

Sets the triggermode for the board.

 

TM_SOFTWARE

0

Sets the trigger mode to software, so that the recording/replay starts immediately.

In addition to the softwaretrigger (free run) it is also possible to force a triggerevent by software while the board is waiting for an internal or external trigger event. Therefore you can use the board command shown in the following table.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board.

 

SPC_FORCETRIGGER

16

Forces a trigger event if the hardware is still waiting for a trigger event. Needs a base board hardware version > 7.x.

Due to the fact that the software trigger is an internal trigger mode, you can optionally enable the external trigger output to generate a high active trigger signal, which indicates when the data acquisition or replay begins. This can be useful to synchronize external equipment with your Spectrum board.

Register

Value

Direction

Description

SPC_TRIGGEROUT

40100

r/w

Defines the data direction of the external trigger connector.

 

0

The trigger connector is not used and the line driver is disabled.

 

1

The trigger connector is used as an output that indicates a detected internal trigger event.

Example for setting up the software trigger:

SpcSetParam

(hDrv,

SPC_TRIGGERMODE,

TM_SOFTWARE);

//

Internal software trigger

mode is

used

SpcSetParam

(hDrv,

SPC_TRIGGEROUT ,

1

);

//

And the trigger output is

enabled

 

 

 

 

 

 

 

 

 

 

External TTL trigger

Enabling the external trigger input is done, if you choose one of the following external trigger modes. The dedicated register for that operation is shown below.

Register

Value

Direction

Description

SPC_TRIGGERMODE

40000

r/w

 

 

TM_TTLPOS

20000

Sets the trigger mode for external TTL trigger to detect positive edges.

 

TM_TTLNEG

20010

Sets the trigger mode for external TTL trigger to detect negative edges

 

 

 

 

 

TM_TTLBOTH

20030

Sets the trigger mode for external TTL trigger to detect positive and negative edges

 

TM_TTLHIGH_LP

20001

Sets the trigger mode for external TTL trigger to detect HIGH pulses that are longer than a programmed pulsewidth.

 

TM_TTLHIGH_SP

20002

Sets the trigger mode for external TTL trigger to detect HIGH pulses that are shorter than a programmed pulsewidth.

 

 

 

 

 

TM_TTLLOW_LP

20011

Sets the trigger mode for external TTL trigger to detect LOW pulses that are longer than a programmed pulsewidth.

 

TM_TTLLOW_SP

20012

Sets the trigger mode for external TTL trigger to detect LOW pulses that are shorter than a programmed pulsewidth.

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MC.31xx Manual

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Page 61 Page 63
Contents MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Inputs Fifo ModeProgramming the Board Standard acquisition modesOption Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/OGeneral Information IntroductionPreface PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationIntroductionHardware information Dynamic ParametersOrder information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Linux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview Software OverviewMicrosoft Visual C++ ++ Driver InterfaceHeader files Borland C++ BuilderDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsInclude Driver Delphi Pascal Programming InterfaceType definition ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterHardware version Installed memoryInstalled features and options Date of productionProgramming the Board Initialization Used interrupt lineUsed type of driver Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog InputsChannel Selection Analog InputsSPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjautoadj Adjall Spcadjsave ADJUSER0Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttriggerMaximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organizationValue ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer valueProgramming Background Fifo Read Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo acquisition modeFifo acquisition example SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generationMinimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Trigger modes and appendant registersGeneral Description External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerTTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulsesSpctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses SpcpulsewidthSpctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers TmchxoffSPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 TmchxoffSPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsOption Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modesSpcmemsize Resulting start delaysTrigger modesOption Multiple Recording SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelOption Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge triggerChannel trigger Example programExample program Option Gated Sampling Spctriggermode TmttlposTimestamp modes StartReset modeOption Timestamp LimitsTimestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Analog Outputs Option Extra I/ODigital I/Os Channel directionProgramming example Programming example Option Extra I/OSample format Bit Standard Mode Digital Inputs enabledOption Digital inputs SpcreaddigitalSynchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubLet the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or triggerDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized runSpcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesError Codes AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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