Spectrum Brands MC.31XX manual Overrange bit, Input termination

Page 45

Analog Inputs

Setting up the inputs

 

 

to the input range of ± 1.0 V. After that the four offset settings are set exactely as the offsets to be compensated, but with the the opposite sign. The result is, that all four channels match perfectely to the choosen input range.

SpcSetParam (hDrv, SPC_AMP0 ,

1000); // Set up channel0 to the range of

± 1.0

V

SpcSetParam (hDrv, SPC_AMP1 ,

1000); // Set up channel1 to the range of

± 1.0

V

SpcSetParam (hDrv, SPC_AMP2 ,

1000); // Set up channel2 to the range of

± 1.0

V

SpcSetParam (hDrv, SPC_AMP3 ,

1000); // Set up channel3 to the range of

± 1.0

V

SpcSetParam (hDrv, SPC_OFFS0,

-100); // Set the input offset to get the

signal symmetrically to 0.0 V

SpcSetParam (hDrv, SPC_OFFS1,

-50);

 

 

SpcSetParam (hDrv, SPC_OFFS2,

50);

 

 

SpcSetParam (hDrv, SPC_OFFS3,

100);

 

 

Overrange bit

With the help of this mode you can additionally record the overrange flag, which is generated by the ADCs. The overrange bit will be stored in bit 15 of the samples. If the signal has been out of range this bit will be set to 1, while a 0 indicates that the sample is within the range.

As the overrange bit is generated from sample to sample by the ADC you have to analyze all the recorded samples to make sure that the range never has been left.

The sample format corresponding with this mode is explained in the according passage in the chapter relating to the acquisition modes. The overrange mode can be enabled by the following register.

Register

Value

Direction

Description

SPC_OVERRANGEBIT

201000

read/write

Enables the recording of the ADC overrange bit in data bit 15. If the bit is not zero the signal has

 

 

 

been out of range.

Input termination

All inputs of Spectrum’s analog boards can be terminated separately with 50 Ohm by software programming. If you do so, please make sure that your signal source is able to deliver the higher output currents. If no termination is used, the inputs have an impedance of 1 Megaohm. The following table shows the corresponding register to set the input termination.

Register

Value

Direction

Description

SPC_50OHM0

30030

r/w

A „1“ sets the 50 ohm termination for channel0. A „0“ sets the termination to1 MOhm.

 

 

 

 

SPC_50OHM1

30130

r/w

A „1“ sets the 50 ohm termination for channel1. A „0“ sets the termination to1 MOhm.

SPC_50OHM2

30230

r/w

A „1“ sets the 50 ohm termination for channel2. A „0“ sets the termination to1 MOhm.

SPC_50OHM3

30330

r/w

A „1“ sets the 50 ohm termination for channel3. A „0“ sets the termination to1 MOhm.

 

 

 

 

SPC_50OHM4

30430

r/w

A „1“ sets the 50 ohm termination for channel4. A „0“ sets the termination to1 MOhm.

SPC_50OHM5

30530

r/w

A „1“ sets the 50 ohm termination for channel5. A „0“ sets the termination to1 MOhm.

SPC_50OHM6

30630

r/w

A „1“ sets the 50 ohm termination for channel6. A „0“ sets the termination to1 MOhm.

 

 

 

 

SPC_50OHM7

30730

r/w

A „1“ sets the 50 ohm termination for channel7. A „0“ sets the termination to1 MOhm.

Automatical adjustment of the offset settings

All of the channels are calibrated in factory before the board is shipped. These settings are stored in the on-board EEProm under the default settings. If you have asymmetrical signals, you can adjust the offset easily with the corresponding registers of the inputs as shown before.

To start the automatic offset adjustment, simply write the register, mentioned in the following table. Because the adjustment of all the channels in all different input ranges can take up some time, it can be useful to adjust only the current input range to safe time.

Before you start an automatic offset adjustment make sure, that no signal is connected to any input. Leave all the input connectors open and then start the adjustment. If you adjust all ranges, this can take up some time. All the internal settings of the driver are changed, while the automatic offset compensation is in progress.

Register

Value

Direction

Description

SPC_ADJ_AUTOADJ

50020

w

Performs the automatic offset compensation in the driver either for all input ranges or only the actual.

 

ADJ_ALL

0

Automatic offset adjustment for all input ranges.

 

ADJ_CURRENT

1

Automatic offset calibration for the current sampling rate setting.

As all settings are temporarily stored in the driver, the automatically adjustment will only affect these values. After exiting your program, all calibration information will be lost. To give you a possibility to save your own settings, every Spectrum card has at minimum one set of user settings that can be saved within the on-board EEPROM. The default settings of the offset and gain values are read-only and cannot be written to the EEProm by the user.

You can easily either save adjustment settings to the EEPROM with SPC_ADJ_SAVE or recall them with SPC_ADJ_LOAD. These two registers are shown in the table below. The values for these EEPROM access registers are the sets that can be stored within the EEPROM. The amount

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Inputs Standard acquisition modesOption Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/OPreface IntroductionGeneral Information PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional optionsTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersIntroductionHardware information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Software Driver Installation Windows InstallationWindows Version controlDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Overview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench Software OverviewHeader files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ BuilderNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsType definition Delphi Pascal Programming InterfaceInclude Driver ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterInstalled features and options Installed memoryHardware version Date of productionUsed type of driver Used interrupt lineProgramming the Board Initialization Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog InputsImportant note on channels selection Analog InputsRerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallProgramming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerCommand register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organizationReading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming General Information Fifo ModeBackground Fifo Read Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsFifo acquisition example Example Fifo acquisition modeSpcfifostart SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generationDirect external clock External clockingMinimum external sample rate Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo General Description Trigger modes and appendant registersSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthOverview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel TmchxoffSpctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffSPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsWhen using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modesTrigger modesOption Multiple Recording Resulting start delaysSpcmemsize SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateAlignement samples per channel End of gate alignementAllowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge triggerExample program Option Gated Sampling Example programChannel trigger Spctriggermode TmttlposOption Timestamp StartReset modeTimestamp modes LimitsFunctions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Digital I/Os Option Extra I/OAnalog Outputs Channel directionProgramming example Option Extra I/O Programming exampleOption Digital inputs Bit Standard Mode Digital Inputs enabledSample format SpcreaddigitalDifferent synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards onlyDefine the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or triggerExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo SpcsyncslavefifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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