Spectrum Brands MC.31XX Example of Fifo buffer allocation, 2a Write first data for output boards

Page 95

Synchronization (Option)

Setup synchronization for use with FIFO mode and equally clokked boards

 

 

Example of FIFO buffer allocation:

for (i = 0; i < FIFO_BUFFERS; i++) for (b = 0; b < 3; b++)

{

pnData[b][i] = (ptr16) GlobalAlloc (GMEM_FIXED, FIFO_BUFLEN); // allocate memory

SpcSetParam (b, SPC_FIFO_BUFADR0 + i, (int32) pnData[b][i]); // send the adress to the driver

}

(2a) Write first data for output boards

When using the synchronization FIFO mode with output boards this is the right position to fill the first software buffers with data. As you can read in the FIFO chapter, output boards need some data to be written to the software FIFO buffers before starting he board.

Example of calulcating and writing output data to software FIFO buffers:

// ----- data calculation routine -----

// some global

variables

int g_nPos =0;

void vCalcOutputData (ptr16 pnData, int32 lBufsize)

// function to

calculate the

{

// output

data. In

this case

int i;

// a sine

function

is used.

for (i = 0; i < (lBufsize/2); i++)

pnData[b][i] = (int16) (8191.0 * sin (2 * PI / 500000 * (g_nPos+i))); g_nPos += lBufsize/2;

}

// ----- main task -----

 

int main(int argc, char **argv)

 

{

 

...

// fill the first buffers with data

for (i =0; i < MAX_BUF; i++)

for (b = 0; b < 3; b++)

// for all installed boards

vCalcOutputData (pnData[b][i], BUFSIZE);

 

...

 

}

 

(6) Define the board for clock master

Using the synchronization option requires one board to be set up as the clock master for all the synchronized board. It is not allowed to set more than one board to clock master.

Register

Value

Direction

Description

 

SPC_COMMAND

0

r/w

Command register of the board

 

 

SPC_SYNCMASTERFIFO

102

Defines the according board as the clock master for operating in FIFO mode only.

Example: board number 0 is clock master

 

 

 

 

 

 

 

 

 

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCMASTERFIFO);

// Set board 0 to clock master

 

 

 

 

 

 

(7) Define the remaining boards as clock slaves

It is necessary to set all the remaining boards to clock slaves to obtain correct internal driver settings.

Register

Value

Direction

Description

 

SPC_COMMAND

0

r/w

Command register of the board

 

 

SPC_SYNCSLAVEFIFO

102

Defines the according board as a clock slave for operating in FIFO mode only.

Settings the remaining boards to clock slaves. Board number 0 is clock master in the example

 

 

 

 

 

 

SpcSetParam (hDrv[1], SPC_COMMAND,

SPC_SYNCSLAVEFIFO);

// Setting all the other boards to

SpcSetParam (hDrv[2], SPC_COMMAND,

SPC_SYNCSLAVEFIFO);

// clock slave is a must !

(9) Start all of the trigger slave boards

After having armed the synchronized boards, you must start all of the boards, that are defined as trigger slaves first. This is done with the FIFOSTART command.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_FIFOSTART

10

Starts the board with the current register settings in FIFO mode and waits for the first interrupt.

Remember that the FIFO mode is allways interrupt driven. As a result the FIFOSTART function will not return until the first software buffer is transferred. For that reason it is absolutely necessary to start different threads

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard acquisition modes Fifo ModeProgramming the Board Analog InputsOption Extra I/O Option Multiple RecordingOption Gated Sampling Option TimestampPreface IntroductionPreface General InformationIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMFTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder No Description Dynamic ParametersOrder information IntroductionHardware informationSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Version control InstallationSoftware Driver Installation Windows WindowsDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Overview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware Overview SoftwareSoftware Overview First Test with SBenchBorland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParamExamples Delphi Pascal Programming InterfaceType definition Include DriverSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineDate of production Installed memoryInstalled features and options Hardware versionDriver version Used interrupt lineUsed type of driver Programming the Board InitializationSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeAnalog Inputs Analog InputsChannel Selection Important note on channels selectionSPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjsave ADJUSER0 Spcadjautoadj AdjallPretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and PosttriggerMinimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit modeValue ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer valueProgramming Speed Limitations Fifo ModeGeneral Information Background Fifo Read60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo acquisition modeFifo acquisition example SpcfifostartSample format Standard internal sample rate Clock generationInternally generated sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clockMaximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rateFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External TTL trigger Trigger modes and appendant registersGeneral Description Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersTTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulsesSpcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode TmttlhighlpTmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode TmchannelSPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 TmchxoffInput ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsRecording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple RecordingSpctriggermode Resulting start delaysTrigger modesOption Multiple Recording SpcmemsizeSpcgate General information and trigger delayOption Gated Sampling Option Gated SamplingAlignement samples per channel End of gate alignementExternal TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modesSpctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel triggerLimits StartReset modeOption Timestamp Timestamp modesReading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp StatusSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Channel direction Option Extra I/ODigital I/Os Analog OutputsProgramming example Option Extra I/O Programming exampleSpcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample formatSynchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger masterArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesRestarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncmasterfifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError Codes Error name Value hex Value dec Error descriptionOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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