Spectrum Brands MC.31XX manual Data format, SpcGetData nr, ch, start, len, data, Spctimestampcount

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Option Timestamp

Reading out timestamp data

 

 

Using this function will not give you back a whole timestamp, as the timestamp values are wider than 32 bit. Please also refer to the section on the timestamp data format below.

Reading out all the timestamps with SpcGetData

When using the function SpcGetData the data stored in the timestamp FIFO will be read out in one block by the driver. The usage of the function SpcGetData is described in the relating section earlier in this manual. The following list does only show the different parameters in a very short way:

SpcGetData (nr, ch, start, len, data)

•nr: Number of the board (Windows). Linux users please refer to the Driver section for differences using linux.

•ch: Channel to be read out. Must be set to CH_TIMESTAMP (9999) to access timestamp FIFO.

•start: [Windows only:] Differing from the standard use, this parameter gives back the number of actually read timestamps and therefore needs to be a pointer. Please refer to the example at the end of this chapter. Under linux please use the SPC_TIMESTAMP_COUNT regis- ter instead and program the „start“ parameter to zero.

•len: Number of timestamps that fit in the data buffer and so defines the number of timestamps to be read out.

•data: Huge buffer for the read out timestamps, that must have at least enough space for 8*len bytes.

It might be that you try to read out more timestamps than there actually are in the timestamp FIFO bacause you don’t know how many trigger events have been detected. Please make use of the value given back by the parameter start to get to know what parts of your buffer contain valid timestamps.

Register

Value

Direction

Description

SPC_TIMESTAMP_COUNT

47020

r

Return the number of timestamps that have been read be the prior SpcGetData call. Needs only to be

 

 

 

used under Linux.

Data format

Each timestamp is 56 bit long and internally mapped to 64 bit (8 bytes). The counter value contains the number of clocks that have been recorded with the currently used sample rate since the last counter-reset has been done. The matching time can easily be calculated as de- scribed in the general information section at the beginning of this chapter.

The values the counter is counting and that are stored in the timestamp FIFO represent the moments the trigger event occures internally. Com- pared to the real external trigger event, these values are delayed. The delay is depending on the actual sample rate, the number of activated channels and the used trigger mode. This delay can be ignored, as it will be identically for all recordings with the same setup.

Timestamp Mode

Recording Mode

1st 4 bytes

2nd 4 bytes

3rd 4 bytes

4th 4 bytes

5th 4 bytes

6th 4 bytes

Standard/StartReset

Normal / Multiple Recording

Trigger 0

Trigger 0

Trigger 1

Trigger 1

Trigger 2

Trigger 2

 

 

LOW part

HIGH part

LOW part

HIGH part

LOW part

HIGH part

Standard/StartReset

Gated Sampling

Gate Start 0

Gate Start 0

Gate End 0

Gate End 0

Gate Start 1

Gate Start 1

 

 

LOW part

HIGH part

LOW part

HIGH part

LOW part

HIGH part

RefClock

Normal / Multiple Recording

Trigger 0

Trigger 0

Trigger 1

Trigger 1

Trigger 2

Trigger 2

 

 

Counter value

Seconds

Counter value

Seconds

Counter value

Seconds

RefClock

Gated Sampling

Gate Start 0

Gate Start 0

Gate End 0

Gate End 0

Gate Start 1

Gate Start 1

 

 

Counter value

Seconds

Counter value

Seconds

Counter value

Seconds

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction SoftwareProgramming the Board Fifo ModeAnalog Inputs Standard acquisition modesOption Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/OPreface IntroductionGeneral Information PrefaceMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 Different models of the MC.31xx seriesIntroduction MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional optionsTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder information Dynamic ParametersIntroductionHardware information Order No DescriptionInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsHardware Installation Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Software Driver Installation Windows InstallationWindows Version controlDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Windows NT Software Driver Installation Windows NTAdding boards to the Windows NT driver Overview LinuxNow it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driverSoftware Overview SoftwareFirst Test with SBench Software OverviewHeader files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ BuilderNational Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsType definition Delphi Pascal Programming InterfaceInclude Driver ExamplesSoftware Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tablesInitialization Example for error checkingStarting the automatic initialization routine PCI RegisterInstalled features and options Installed memoryHardware version Date of productionUsed type of driver Used interrupt lineProgramming the Board Initialization Driver versionExample program for the board initialization Powerdown and resetSpcpcimemsize SpcpciserialnoChannel Selection Analog InputsImportant note on channels selection Analog InputsRerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetOverrange bit Automatical adjustment of the offset settingsInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallProgramming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerCommand register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStandard acquisition modes Programming Starting with interrupt driven modeStatus register Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organizationReading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming General Information Fifo ModeBackground Fifo Read Speed LimitationsSoftware Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersBuffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsFifo acquisition example Example Fifo acquisition modeSpcfifostart SpcfifowaitSample format Internally generated sample rate Clock generationStandard internal sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generationDirect external clock External clockingMinimum external sample rate Maximum external samplerate in MS/sCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerFifo General Description Trigger modes and appendant registersSoftware trigger External TTL triggerEdge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL triggerPositive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthOverview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel TmchxoffSpctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffSPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short negative pulses Channel pulsewidth trigger for short positive pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsWhen using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modesTrigger modesOption Multiple Recording Resulting start delaysSpcmemsize SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateAlignement samples per channel End of gate alignementAllowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge triggerExample program Option Gated Sampling Example programChannel trigger Spctriggermode TmttlposOption Timestamp StartReset modeTimestamp modes LimitsFunctions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp dataSpcGetData nr, ch, start, len, data Data formatSpctimestampcount Example programs Standard acquisition modeAcquisition with Multiple Recording Digital I/Os Option Extra I/OAnalog Outputs Channel directionProgramming example Option Extra I/O Programming exampleOption Digital inputs Bit Standard Mode Digital Inputs enabledSample format SpcreaddigitalDifferent synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhubSet up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards onlyDefine the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or triggerExample board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationWait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo SpcsyncslavefifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorOption Digital inputs Pin assignment of the multipin cable
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