Spectrum Brands MC.31XX manual End of gate alignement, Alignement samples per channel

Page 80

Trigger modes

Option Gated Sampling

 

 

the number of acquired samples will be less than the gate signal length. See table on the next page for further explanation.

End of gate alignement

Due to the structure of the on-board memory there is an- other delay at the end of the gate interval.

Internally a gate-end signal can only be recognized at an eight samples alignment. This alignement is a sum of all channels that are activated together. Please refer to the following chapter to see the alignement for each channel and mode combination.

So depending on what time your external gate signal will leave the programmed gate condition it might hap- pen that at maximum seven more samples are recorded, before the board pauses (see figure).

The figure on the right is showing this end delay exem- plarily for three possible gate signals. As all samples are counted from zero. The eight samples alignment in the upper two cases is reached at the end of sample 39, which is therefore the 40th sample.

Alignement samples per channel

As described above there’s an alignement at the end of the gate signal. The alignement depends on the used mode (standard or FIFO) and the selected channels. Please refer to this table to see how many samples per channel of alignement one gets.

Module 0

 

 

Module 1

 

 

 

 

0

1

2

3

0

1

2

3

Mode

Alignement

X

 

 

 

 

 

 

 

Standard/FIFO

8 samples

X

 

 

 

X

 

 

 

Standard

8 samples

X

 

 

 

X

 

 

 

FIFO

4 samples

X

X

 

 

 

 

 

 

Standard/FIFO

4 samples

X

X

 

 

X

X

 

 

Standard

4 samples

X

X

 

 

X

X

 

 

FIFO

2 samples

X

X

X

X

 

 

 

 

Standard/FIFO

2 samples

X

X

X

X

X

X

X

X

Standard

2 samples

X

X

X

X

X

X

X

X

FIFO

1 sample

80

MC.31xx Manual

Page 79 Page 81
Image 80
Page 79 Page 81
Contents MC.31xx English version April 27Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Inputs Standard acquisition modesOption Multiple Recording Option Gated SamplingOption Timestamp Option Extra I/OIntroduction PrefaceGeneral Information PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Additional options Digital inputsExtra I/O Option -XMF Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationIntroductionHardware information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Installation Software Driver Installation WindowsWindows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Linux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software Overview++ Driver Interface Header filesMicrosoft Visual C++ Borland C++ BuilderOther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversSoftware ++ Driver Interface Using the Driver under Linux Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsDelphi Pascal Programming Interface Type definitionInclude Driver ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Installed features and optionsHardware version Date of productionUsed interrupt line Used type of driverProgramming the Board Initialization Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Inputs Channel SelectionImportant note on channels selection Analog InputsChannel rerouting Rerouting information for moduleSPCCHROUTE0 SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjautoadj Adjall Spcadjsave ADJUSER0Standard acquisition modes ProgrammingMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerStarting without interrupt classic mode Command registerMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming Normal mode Fast 8 bit mode201100 Enables the fast 8 bit mode Data organizationStandard mode Reading out the data with SpcGetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming Fifo Mode General InformationBackground Fifo Read Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo acquisition mode Fifo acquisition exampleSpcfifostart SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate Using plain quartz without PLL Maximum internal sample rate in MS/s normal modeExternal reference clock Clock generationExternal clocking Direct external clockMinimum external sample rate Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Trigger modes and appendant registers General DescriptionSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPulsewidth triggers Positive and negative TTL triggerTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for long LOW pulses TTL pulsewidth trigger for short LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthChannel Trigger Overview of the channel trigger registersSpctriggermode Tmchannel TmchxoffTriggerlevel Spctriggermode TmchorSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffReading out the number of possible trigger levels SPCTRIGGERMODE0 TmchxposSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVDetailed description of the channel trigger modes Channel trigger on positive edgeChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsStandard Mode When using Multiple Recording pretrigger is not availableOption Multiple Recording Recording modesResulting start delays Trigger modesOption Multiple RecordingSpcmemsize SpctriggermodeGeneral information and trigger delay Option Gated SamplingOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelNumber of samples on gate signal Allowed trigger modesOption Gated SamplingTrigger modes External TTL edge triggerExample program Example program Option Gated SamplingChannel trigger Spctriggermode TmttlposStartReset mode Option TimestampTimestamp modes LimitsRefClock mode optional Functions for accessing the dataTimestamp Status Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Option Extra I/O Digital I/OsAnalog Outputs Channel directionProgramming example Programming example Option Extra I/OBit Standard Mode Digital Inputs enabled Option Digital inputsSample format SpcreaddigitalSynchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersLet the master calculate it’s clocking Write Data to on-board memory output boards onlyExample for data writing Define the boards for trigger masterExample of board #2 set as trigger master 4a Define synchronization or triggerDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Restarting the board for another synchronized runExample of Fifo buffer allocation 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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