Spectrum Brands MC.31XX Buffer processing, Fifo Mode Programming, Digital I/O board 7005 only

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FIFO Mode

 

 

 

 

Programming

 

 

 

 

 

 

Analog acquisition or generation boards

 

 

 

 

 

 

Buffer length to be programmed in Bytes

 

 

 

 

 

 

 

 

 

8 bit resolution

12 bit resolution

14 bit resolution

16 bit resolution

1

Channel

1 x [Samples in Buffer]

1 x 2 x [Samples in Buffer]

1 x 2 x [Samples in Buffer]

1 x 2 x [Samples in Buffer]

 

2

Channels

2 x [Samples in Buffer]

2 x 2 x [Samples in Buffer]

2 x 2 x [Samples in Buffer]

2 x 2 x [Samples in Buffer]

4

Channels

4 x [Samples in Buffer]

4 x 2 x [Samples in Buffer]

4 x 2 x [Samples in Buffer]

4 x 2 x [Samples in Buffer]

8

Channels

8 x [Samples in Buffer]

8 x 2 x [Samples in Buffer]

8 x 2 x [Samples in Buffer]

8 x 2 x [Samples in Buffer]

Digital I/O (701x or 702x ) or pattern generator boards (72xx)

 

 

Buffer length to be programmed in Bytes

 

 

 

8 bit mode

16 bit mode

 

32 bit mode

64 bit mode

 

 

[Samples in Buffer]

2 x [Samples in Buffer]

 

4 x [Samples in Buffer]

8 x [Samples in Buffer]

 

Digital I/O board 7005 only

 

 

 

 

 

 

 

 

Buffer length to be programmed in Bytes

 

 

 

 

 

 

1 bit mode

2 bit mode

 

4 bit mode

8 bit mode

16 bit mode

1 Channel

1/8 x [Samples in Buffer]

1/4 x [Samples in Buffer]

 

1/2 x [Samples in Buffer]

[Samples in Buffer]

2 x [Samples in Buffer]

We at Spectrum achieved best results when programming the buffer length to a number of samples that can hold approximately 100 ms of data. However if going to the limit of the PCI bus with the FIFO mode or when having buffer overruns it can be useful to have larger FIFO buffers to buffer more data in it.

When the goal is a fast update in FIFO mode smaller buffers and a larger number of buffers can be a better setup.

Register

Value

Direction

Description

SPC_FIFO_BUFADR0

60100

r/w

32 bit address of FIFO buffer 0. Must be allocated by application program

SPC_FIFO_BUFADR1

60101

r/w

32 bit address of FIFO buffer 1. Must be allocated by application program

 

 

 

 

...

 

 

...

 

 

 

 

SPC_FIFO_BUFADR255

60355

r/w

32 bit address of FIFO buffer 255. Must be allocated by application program

The driver handles the programmed number of buffers. To speed up FIFO transfer the driver uses buffers that are allocated and maintained by the application program. Before starting the FIFO mode the addresses of the allocated buffers must be set to the driver.

Example of FIFO buffer setup. No memory allocation error checking in the example to improve readability:

// -----

setup FIFO buffers -----

64);

// 64 FIFO buffers used in the example

SpcSetParam

(hDrv, SPC_FIFO_BUFFERS,

SpcSetParam

(hDrv, SPC_FIFO_BUFLEN,

8192);

// Each FIFO buffer is 8 kBytes long

// -----

allocate memory for data -----

 

 

for (i =

0;

i < 64; i++)

 

// memory allocation for 12, 14, 16 bit analog boards

pnData[i] = (ptr16) malloc (8192);

 

// pbyData[i] = (ptr8) malloc (8192);

 

// and digital boards

 

// memory allocation for 8 bit analog boards

// -----

tell the used buffer adresses to the driver -----

for (i =

0;

i < 64; i++)

 

 

nErr = SpcSetParam (hDrv, SPC_FIFO_BUFADR0 + i,

(int32) pnData[i]); // for 12, 14, 16 bit analog boards

// nErr = SpcSetParam (hDrv, SPC_FIFO_BUFADR0 + i,

// and digital boards only

(int32) pbyData[i]); // for 8 bit analog boards only

Buffer processing

The driver counts all the software buffers that have been transferred. This number can be read out from the driver to know the exact amount of data that has been transferred.

Register

Value

Direction

Description

SPC_FIFO_BUFCOUNT

60020

r

Number of transferred buffers until now

If one knows before starting FIFO mode how long this should run it is possible to program the numer of buffers that the driver should process. After transferring this number of buffer the driver will automatically stop. If FIFO mode should run endless a zero must be programmed to this register. Then the FIFO mode must be stoped by the user.

Register

Value

Direction

Description

SPC_FIFO_BUFMAXCNT

60030

r/w

Number of buffers to be transferred until automatic stop. Zero runs endless

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard acquisition modes Fifo ModeProgramming the Board Analog InputsOption Extra I/O Option Multiple RecordingOption Gated Sampling Option TimestampPreface IntroductionPreface General InformationMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 Different models of the MC.31xx seriesIntroduction MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMFTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder No Description Dynamic ParametersOrder information IntroductionHardware informationInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsHardware Installation Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Version control InstallationSoftware Driver Installation Windows WindowsDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Windows NT Software Driver Installation Windows NTAdding boards to the Windows NT driver Overview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware Overview SoftwareSoftware Overview First Test with SBenchBorland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParamExamples Delphi Pascal Programming InterfaceType definition Include DriverSoftware Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineDate of production Installed memoryInstalled features and options Hardware versionDriver version Used interrupt lineUsed type of driver Programming the Board InitializationSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeAnalog Inputs Analog InputsChannel Selection Important note on channels selectionSPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetOverrange bit Automatical adjustment of the offset settingsInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallPretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and PosttriggerMinimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamplesStandard acquisition modes Programming Starting with interrupt driven modeStatus register Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit modeValue ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer valueProgramming Speed Limitations Fifo ModeGeneral Information Background Fifo Read60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo acquisition modeFifo acquisition example SpcfifostartSample format Internally generated sample rate Clock generationStandard internal sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clockMaximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rateCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerFifo External TTL trigger Trigger modes and appendant registersGeneral Description Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersTTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulsesSpcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode TmttlhighlpTmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode TmchannelSPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 TmchxoffInput ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short negative pulses Channel pulsewidth trigger for short positive pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsRecording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple RecordingSpctriggermode Resulting start delaysTrigger modesOption Multiple Recording SpcmemsizeSpcgate General information and trigger delayOption Gated Sampling Option Gated SamplingAlignement samples per channel End of gate alignementExternal TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modesSpctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel triggerLimits StartReset modeOption Timestamp Timestamp modesReading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp StatusSpcGetData nr, ch, start, len, data Data formatSpctimestampcount Example programs Standard acquisition modeAcquisition with Multiple Recording Channel direction Option Extra I/ODigital I/Os Analog OutputsProgramming example Option Extra I/O Programming exampleSpcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample formatSynchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger masterArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesRestarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncmasterfifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError Codes Error name Value hex Value dec Error descriptionExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorOption Digital inputs Pin assignment of the multipin cable
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