Spectrum Brands MC.31XX manual Data organization, Sample format, Normal mode, Fast 8 bit mode

Page 50

Programming

Standard acquisition modes

 

 

Data organization

Normal mode

This chapter shows the data organization for all acquisitions that are done with the normal data width of 12 bit. The data organization for the fast 8 bit mode is described in the next passage.

In standard mode tha data is organized on the board in two memory channels, named memory channel 0 and memory channel 1. The data in memory is organized depending on the used channels and the type of board. This is a result of the internal hardware structure of the board.

Ch0

Ch1

Ch2

Ch3

Ch4

Ch5

Ch6

Ch7

Sample ordering in standard mode on memory channel 0

Sample ordering in standard mode on memory channel 1

X

 

 

 

 

 

 

 

A0

A1

A2

A3

A4

A5

A6

A7

 

 

 

 

 

 

 

 

X

X

 

 

 

 

 

 

A0

B0

A1

B1

A2

B2

A3

B3

 

 

 

 

 

 

 

 

X

 

 

 

x

 

 

 

A0

A1

A2

A3

A4

A5

A6

A7

E0

E1

E2

E3

E4

E5

E6

E7

X

X

 

 

X

X

 

 

A0

B0

A1

B1

A2

B2

A3

B3

E0

F0

E1

F1

E2

F2

E3

F3

X

X

X

X

 

 

 

 

A0

B0

C0

D0

A1

B1

C1

D1

 

 

 

 

 

 

 

 

X

X

X

X

X

X

X

X

A0

B0

C0

D0

A1

B1

C1

D1

E0

F0

G0

H0

E1

F1

G1

H1

The samples are re-named for better readability. A0 is sample 0 of channel 0, C4 is sample 4 of channel 2, ...

Fast 8 bit mode

The fast 8 bit mode allows you to sample two channels that are located on one interface module, with a reduced 8 bit resolution and write the data to one combined 16 bit sample. This mode can be used to

•record longer signals in Standard mode as each sample only occupies one Byte instead of 2 Bytes with 12-bit resolution, or

•use more channels and/or increased sample rate in FIFO mode, as the required data transfer rate is reduced by 50 %.

To set up the board for this mode you must enable it with the following register.

Register

Value

Direction

Description

SPC_2CH8BITMODE

201100

r/w

Enables the fast 8 bit mode.

You must set up the channels the same way as if you want to activate only one or two (ch0 and ch1) channels per module. If more channels are enabled, this mode won’t work correctly.

The data organization is not different regarding the sample order from the normal mode with only one (or two) channels per module enabled. The only difference is, that one 16 bit sample now consists of two 8 bit samples. For details on the sample format please refer to the related passage in this chapter. The following table shows, how the data is stored.

Activated channels (see important note above)

 

 

 

 

 

 

 

 

 

 

 

 

 

Ch0

Ch1

Ch2

Ch3

Ch4

Ch5

Ch6

Ch7

Sample ordering in fast 8 bit mode on memory channel 0

Sample ordering in fast 8 bit mode on memory channel 1

X

 

 

 

 

 

 

 

B0/A0

B1/A1

B2/A2

B3/A3

B4/A4

B5/A5

 

 

 

 

 

 

X

X

 

 

 

 

 

 

B0/A0

D0/C0

B1/A1

D1/C1

B2/A2

D2/C2

 

 

 

 

 

 

X

 

 

 

x

 

 

 

B0/A0

B1/A1

B2/A2

B3/A3

B4/A4

B5/A5

F0/E0

F1/E1

F2/E2

F3/E3

F4/E4

F5/E5

X

X

 

 

X

X

 

 

B0/A0

D0/C0

B1/A1

D1/C1

B2/A2

D2/C2

F0/E0

H0/G0

F1/E1

H1/G1

F2/E2

H2/G2

Sample format

The 12 bit samples in twos complement are always stored in memory as sign extended 16 bit integer values. This leads to a range of possible integer values from -2048…0…+2047.

If the overrange mode is enabled the upper bit is used for the overrange bit except for the sign extension. Therefore it is not possible to use the samples for calculations, without removing the overrange bit.

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MC.31xx Manual

Page 49 Page 51
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Page 49 Page 51
Contents MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Inputs Fifo ModeProgramming the Board Standard acquisition modesOption Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/OGeneral Information IntroductionPreface PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationIntroductionHardware information Dynamic ParametersOrder information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Linux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview Software OverviewMicrosoft Visual C++ ++ Driver InterfaceHeader files Borland C++ BuilderDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsInclude Driver Delphi Pascal Programming InterfaceType definition ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterHardware version Installed memoryInstalled features and options Date of productionProgramming the Board Initialization Used interrupt lineUsed type of driver Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog InputsChannel Selection Analog InputsSPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjautoadj Adjall Spcadjsave ADJUSER0Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttriggerMaximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organizationValue ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer valueProgramming Background Fifo Read Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo acquisition modeFifo acquisition example SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generationMinimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Software trigger Trigger modes and appendant registersGeneral Description External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerTTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulsesSpctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses SpcpulsewidthSpctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers TmchxoffSPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 TmchxoffSPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsOption Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modesSpcmemsize Resulting start delaysTrigger modesOption Multiple Recording SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelOption Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge triggerChannel trigger Example programExample program Option Gated Sampling Spctriggermode TmttlposTimestamp modes StartReset modeOption Timestamp LimitsTimestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Analog Outputs Option Extra I/ODigital I/Os Channel directionProgramming example Programming example Option Extra I/OSample format Bit Standard Mode Digital Inputs enabledOption Digital inputs SpcreaddigitalSynchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubLet the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or triggerDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized runSpcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesError Codes AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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