Spectrum Brands MC.31XX manual Software Buffers, Programming Fifo Mode

Page 54

Programming

FIFO Mode

 

 

 

 

Theoretical maximum sample rate

PCI Bus Throughput

1

Channel

50 MS/s

[1 Channel] x [2 Bytes per sample] * 50 MS/s = 100 MB/s

2

Channels

25 MS/s

[2 Channels] x [2 Bytes per sample] * 25 MS/s = 100 MB/s

4

Channels

12.5 MS/s

[4 Channels] x [2 Bytes per sample] * 12.5 MS/s = 100 MB/s

8

Channels

6.25 MS/s

[8 Channels] x [2 Bytes per sample] * 6.25 MS/s = 100 MB/s

When using FIFO mode together with one of the options that allow to have gaps in the acquisiton like Multiple Recording or Gated Sampling one can even run the board with higher sample rates. It just has to be sure that the average sample rate (calculated with acquisition time and gap) does not exceed the above mentioned sample rate limitations.

The sample rate that can be run in one of these mode is depending on the number of channels that have been activated. Due to the internal structure of the board this is limited to a internal throughput of 250 MB/s (125 MS/s):

 

 

Maximum sample rate that can be programmed

Internal throughput

1

Channel

125 MS/s

[1 Channel] x [2 Bytes per sample] x 125 MS/s = 250 MB/s

2

Channels

62.5 MS/s

[2 Channels] x [2 Bytes per sample] x 62.5 MS/s = 250 MB/s

4

Channels

31.25 MS/s

[4 Channels] x [2 Bytes per sample] x 31.25 MS/s = 250 MB/s

8

Channels

15.625 MS/s

[8 Channels] x [2 Bytes per sample] x 15.625 MS/s = 250 MB/s

Programming

The setup of FIFO mode is done with a few additional software registers described in this chapter. All the other settings can be used as de- scribed before. In FIFO mode the register SPC_MEMSIZE and SPC_POSTTRIGGER are not used.

Software Buffers

This register defines the number of software buffers that should be used for FIFO mode. The number of hardware buffers is always two and can not be changed by software.

Register

Value

Direction

Description

SPC_FIFO_BUFFERS

60000

r/w

Number of software buffers to be used for FIFO mode. Value has to be between 2 and 256

When this manual was printed there are a total of 256 buffers possible. However if there are changes and enhancements to the driver in the future it will be informative to read out the number of buffers the new driver version can hold.

Register

Value

Direction

Description

SPC_FIFO_BUFADRCNT

60040

r

Read out the number of available FIFO buffers

The length of each buffer is defined in bytes. This length is used for hardware and software buffers as well. Both have the same length. The maximum length that can be used is depending on the installed on-board memory.

Register

Value

Direction

Description

SPC_FIFO_BUFLEN

60010

r/w

Length of each buffer in bytes. Must be a multiple of 1024 bytes.

Each FIFO buffer can be a maximum of half the memory. Be aware that the buffer length is given in overall bytes not in samples. Therefore the value has to be calculated depending on the activated channels and the resolution of the board:

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MC.31xx Manual

Page 53 Page 55
Image 54
Page 53 Page 55
Contents MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Inputs Fifo ModeProgramming the Board Standard acquisition modesOption Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/OGeneral Information IntroductionPreface PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationIntroductionHardware information Dynamic ParametersOrder information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview Software OverviewMicrosoft Visual C++ ++ Driver InterfaceHeader files Borland C++ BuilderDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsInclude Driver Delphi Pascal Programming InterfaceType definition ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterHardware version Installed memoryInstalled features and options Date of productionProgramming the Board Initialization Used interrupt lineUsed type of driver Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog InputsChannel Selection Analog InputsSPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttriggerMaximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organizationValue ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer valueProgramming Background Fifo Read Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo acquisition modeFifo acquisition example SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generationMinimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Software trigger Trigger modes and appendant registersGeneral Description External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerTTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulsesSpctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses SpcpulsewidthSpctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers TmchxoffSPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 TmchxoffSPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsOption Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modesSpcmemsize Resulting start delaysTrigger modesOption Multiple Recording SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelOption Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge triggerChannel trigger Example programExample program Option Gated Sampling Spctriggermode TmttlposTimestamp modes StartReset modeOption Timestamp LimitsTimestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Analog Outputs Option Extra I/ODigital I/Os Channel directionProgramming example Programming example Option Extra I/OSample format Bit Standard Mode Digital Inputs enabledOption Digital inputs SpcreaddigitalSynchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubLet the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or triggerDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized runSpcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesError Codes AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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