Spectrum Brands MC.31XX manual Hardware information, Block diagram Technical Data

Page 12

Hardware information	Introduction

Hardware information

Block diagram

Technical Data

Resolution

12 bit

Dimension

160 x 233 mm (Standard 6U)

Differential linearity error

≤ 1 LSB (ADC)

Width (Standard)

1 slot

Integral linearity error

≤ 2.5 LSB (ADC)

Width (with digital inputs)

2 slots

Multi: Trigger to 1st sample delay

fix

Connector

3 mm SMB male

Multi: Recovery time

< 20 samples

Input impedance

50 Ohm / 1 MOhm 25 pF

ext. Trigger accuracy

1 Samples

Overvoltage protection (range ≤ ±1 V)

±5 V

int. Trigger accuracy

1 Sample

Overvoltage protection (range > ±1 V)

±50 V

Ext. clock: delay to internal clock

42 ns ±2 ns

Warm up time

10 minutes

input signal with 50 ohm termination

max 5 V rms

Operating temperature

0°C - 50°C

Digital Inputs input impedance

110 Ohm @ 2.5 V

Storage temperature

-10°C - 70°C

Digital Inputs delay to analog sample

-4 samples

Humidity

10% to 90%

Min internal clock

1 kS/s

Min external clock

1 kS/s

Power consumption 5 V @

full speed

max. 3.3 A (16.5 Watt)

Power consumption 5 V @ power down

max. 2.5 A (12.5 Watt)

Trigger input:Standard TTL level

Low: -0.5 > level < 0.8 V

Clock input: Standard TTL level

Low: -0.5 V > level < 0.8 V

High: 2.0 V > level < 5.5 V

High: 2.0 V > level < 5.5 V

Trigger pulse must be valid > 2 clock periods.

Rising edge. Duty cycle: 50% ± 5%

Trigger output

Standard TTL, capable of driving 50 Ohm.

Clock output

Standard TTL, capable of driving 50 Ohm

Low < 0.4 V (@ 20 mA, max 64 mA)

Low < 0.4 V (@ 20 mA, max 64 mA)

High > 2.4 V (@ -20 mA, max -48 mA)

High > 2.4 V (@ -20 mA, max -48 mA)

One positive edge after the first internal trigger

Input range

±50 mV

±100 mV

±200 mV

±500 mV

±1 V

±2 V

±5 V

±10 V

Software programmable offset

±50 mV

±100 mV

±200 mV

±500 mV

±1 V

±2 V

±5 V

±10 V

Offset error

< 1 LSB, adjustable by user

Gain error

< 1 %

< 1 %

< 1 %

< 1 %

< 1 %

< 1 %

< 1 %

< 1 %

Noise (rms): 50 Ohm, 25 MS/s

< 1.5 LSB

< 1.2 LSB

< 1.0 LSB

< 1.0 LSB

< 1.0 LSB

< 1.0 LSB

< 1.0 LSB

< 1.0 LSB

Crosstalk 500 kHz signal, ±50 mV input, 50 Ohm

< -70 dB

MC.3110

MC.3112

MC.3120

MC.3122

MC.3130

MC.3132

MC.3111

MC.3121

MC.3131

max internal clock

1 MS/s

1 MS/s

10 MS/s

10 MS/s

25 MS/s

25 MS/s

max external clock

1 MS/s

1 MS/s

10 MS/s

10 MS/s

25 MS/s

25 MS/s

-3 dB bandwidth

> 500 kHz

> 500 kHz

> 5 MHz

> 5 MHz

> 12.5 MHz

> 12.5 MHz

12	MC.31xx Manual

Image 12

Contents MC.31xx English version April 27Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Inputs Standard acquisition modesOption Multiple Recording Option Gated SamplingOption Timestamp Option Extra I/OIntroduction PrefaceGeneral Information PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Additional options Digital inputsExtra I/O Option -XMF Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationIntroductionHardware information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Installation Software Driver Installation WindowsWindows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software Overview++ Driver Interface Header filesMicrosoft Visual C++ Borland C++ BuilderOther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversSoftware ++ Driver Interface Using the Driver under Linux Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsDelphi Pascal Programming Interface Type definitionInclude Driver ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Installed features and optionsHardware version Date of productionUsed interrupt line Used type of driverProgramming the Board Initialization Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Inputs Channel SelectionImportant note on channels selection Analog InputsChannel rerouting Rerouting information for moduleSPCCHROUTE0 SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0Standard acquisition modes ProgrammingMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerStarting without interrupt classic mode Command registerMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Normal mode Fast 8 bit mode201100 Enables the fast 8 bit mode Data organizationStandard mode Reading out the data with SpcGetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming Fifo Mode General InformationBackground Fifo Read Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo acquisition mode Fifo acquisition exampleSpcfifostart SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz without PLL Maximum internal sample rate in MS/s normal modeExternal reference clock Clock generationExternal clocking Direct external clockMinimum external sample rate Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Trigger modes and appendant registers General DescriptionSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPulsewidth triggers Positive and negative TTL triggerTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for long LOW pulses TTL pulsewidth trigger for short LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthChannel Trigger Overview of the channel trigger registersSpctriggermode Tmchannel TmchxoffTriggerlevel Spctriggermode TmchorSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffReading out the number of possible trigger levels SPCTRIGGERMODE0 TmchxposSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVDetailed description of the channel trigger modes Channel trigger on positive edgeChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsStandard Mode When using Multiple Recording pretrigger is not availableOption Multiple Recording Recording modesResulting start delays Trigger modesOption Multiple RecordingSpcmemsize SpctriggermodeGeneral information and trigger delay Option Gated SamplingOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelNumber of samples on gate signal Allowed trigger modesOption Gated SamplingTrigger modes External TTL edge triggerExample program Example program Option Gated SamplingChannel trigger Spctriggermode TmttlposStartReset mode Option TimestampTimestamp modes LimitsRefClock mode optional Functions for accessing the dataTimestamp Status Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Option Extra I/O Digital I/OsAnalog Outputs Channel directionProgramming example Programming example Option Extra I/OBit Standard Mode Digital Inputs enabled Option Digital inputsSample format SpcreaddigitalSynchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersLet the master calculate it’s clocking Write Data to on-board memory output boards onlyExample for data writing Define the boards for trigger masterExample of board #2 set as trigger master 4a Define synchronization or triggerDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Restarting the board for another synchronized runExample of Fifo buffer allocation 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable