Spectrum Brands MC.31XX External clocking, Direct external clock, Minimum external sample rate

Page 60

External clocking

Clock generation

 

 

External clocking

Direct external clock

An external clock can be fed in on the external clock connector of the board. This can be any clock, that matches the specification of the card. The external clock signal can be used to synchronize the card on a system clock or to feed in an exact matching sample rate.

Register

Value

Direction

Description

SPC_EXTERNALCLOCK

20100

read/write

Enables the external clock input. If external clock input is disabled, internal clock will be used.

The maximum values for the external clock is board dependant and shown in the table below.

Termination of the clock input

If the external connector is used as an input, either for feeding in an external reference clock or for external clocking you can enable a 50 Ohm termination on the board. If the termination is disabled, the impedance is high. Please make sure that your source is capable of driving that current and that it still fulfills the clock input specification as given in the technical data section.

Register

Value

Direction

Description

SPC_CLOCK50OHM

20120

read/write

A „1“ enables the 50 Ohm termination at the external clock connector. Only possible, when using

 

 

 

the external connector as an input.

Minimum external sample rate

The minimum external sample rate is limited on all boards to 1 kHz and the maximum sample rate depends on the specific type of board. The maximum sample rates for your type of board are shown in the tables below.

Maximum external samplerate in MS/s

Remapped channels

 

 

 

 

3110

3111

3112

3120

3121

3122

3130

3131

3132

3140

ch0

ch1

ch2

ch3

ch4

ch5

ch6

ch7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

 

 

 

 

 

 

 

1

1

1

10

10

10

25

25

25

50

x

x

 

 

 

 

 

 

1

1

1

10

10

10

25

25

25

25

x

 

 

 

x

 

 

 

n.a.

n.a.

1

n.a.

n.a.

10

n.a.

n.a.

25

n.a.

x

x

 

 

x

x

 

 

n.a.

n.a.

1

n.a.

n.a.

10

n.a.

n.a.

25

n.a.

x

x

x

x

 

 

 

 

n.a.

1

1

n.a.

10

10

n.a.

25

25

n.a.

x

x

x

x

x

x

x

x

n.a.

n.a.

1

n.a.

n.a.

10

n.a.

n.a.

25

n.a.

An external sample rate above the mentioned maximum can cause damage to the board.

Ranges for external sample rate

Due to the internal structure of the board it is essential to know for the driver in which clock range the external clock is operating. The external range register must be set according to the clock that is fed in externally.

Register

Value

Direction

Description

SPC_EXTERNRANGE

20130

r/w

Defines the range of the actual fed in external clock. Use one of the below mentioned ranges

 

EXRANGE_SINGLE

2

External Range Single

 

EXRANGE_BURST_S

4

External Range Burst S

 

 

 

 

 

EXRANGE_BURST_M

8

External Range Burst M

 

EXRANGE_BURST_L

16

External Range Burst X

 

EXRANGE_BURST_XL

32

External Range Burst XL

The range must not be left by more than 5 % when the board is running. Remember that the ranges depend on the activated channels as well, so a different board setup for external clocking must always include the related clock ranges.

This table below shows the ranges that are defined by the different range registers mentioned above. The range depends on the activated channels and the mode the board is used in. Please be sure to select the correct range. Otherwise it is possible that the board will not run properly.

60

MC.31xx Manual

Page 59 Page 61
Image 60
Page 59 Page 61
Contents MC.31xx English version April 27Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Inputs Standard acquisition modesOption Multiple Recording Option Gated SamplingOption Timestamp Option Extra I/OIntroduction PrefaceGeneral Information PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Additional options Digital inputsExtra I/O Option -XMF Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationIntroductionHardware information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Installation Software Driver Installation WindowsWindows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software Overview++ Driver Interface Header filesMicrosoft Visual C++ Borland C++ BuilderOther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversSoftware ++ Driver Interface Using the Driver under Linux Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsDelphi Pascal Programming Interface Type definitionInclude Driver ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Installed features and optionsHardware version Date of productionUsed interrupt line Used type of driverProgramming the Board Initialization Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Inputs Channel SelectionImportant note on channels selection Analog InputsChannel rerouting Rerouting information for moduleSPCCHROUTE0 SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0Standard acquisition modes ProgrammingMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerStarting without interrupt classic mode Command registerMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Normal mode Fast 8 bit mode201100 Enables the fast 8 bit mode Data organizationStandard mode Reading out the data with SpcGetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming Fifo Mode General InformationBackground Fifo Read Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo acquisition mode Fifo acquisition exampleSpcfifostart SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz without PLL Maximum internal sample rate in MS/s normal modeExternal reference clock Clock generationExternal clocking Direct external clockMinimum external sample rate Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Trigger modes and appendant registers General DescriptionSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPulsewidth triggers Positive and negative TTL triggerTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for long LOW pulses TTL pulsewidth trigger for short LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthChannel Trigger Overview of the channel trigger registersSpctriggermode Tmchannel TmchxoffTriggerlevel Spctriggermode TmchorSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffReading out the number of possible trigger levels SPCTRIGGERMODE0 TmchxposSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVDetailed description of the channel trigger modes Channel trigger on positive edgeChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsStandard Mode When using Multiple Recording pretrigger is not availableOption Multiple Recording Recording modesResulting start delays Trigger modesOption Multiple RecordingSpcmemsize SpctriggermodeGeneral information and trigger delay Option Gated SamplingOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelNumber of samples on gate signal Allowed trigger modesOption Gated SamplingTrigger modes External TTL edge triggerExample program Example program Option Gated SamplingChannel trigger Spctriggermode TmttlposStartReset mode Option TimestampTimestamp modes LimitsRefClock mode optional Functions for accessing the dataTimestamp Status Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Option Extra I/O Digital I/OsAnalog Outputs Channel directionProgramming example Programming example Option Extra I/OBit Standard Mode Digital Inputs enabled Option Digital inputsSample format SpcreaddigitalSynchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersLet the master calculate it’s clocking Write Data to on-board memory output boards onlyExample for data writing Define the boards for trigger masterExample of board #2 set as trigger master 4a Define synchronization or triggerDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Restarting the board for another synchronized runExample of Fifo buffer allocation 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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