Spectrum Brands MC.31XX manual Example for data writing, Define the boards for trigger master

Page 92

The setup order for the different synchronization options

Synchronization (Option)

 

 

Example for data writing

SpcSetData (hDrv[0], 0, 0, 1024, pData[0]);

SpcSetData (hDrv[1], 0, 0, 1024, pData[1]);

SpcSetData (hDrv[2], 0, 0, 1024, pData[2]);

(4) Define the board(s) for trigger master

At least one board must be set as the trigger master to get synchronization running. Every one of the synchronized boards can be programmed for beeing the trigger master device.

Register

Value

Direction

Description

 

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_SYNCTRIGGERMASTER

101

Defines the according board as the triggermaster.

Example of board #2 set as trigger master

 

 

 

 

 

 

 

 

 

SpcSetParam (hDrv[2], SPC_COMMAND,

SPC_SYNCTRIGGERMASTER);

// Set board 2 to trigger master

 

 

 

 

 

 

(4a) Define synchronization OR trigger

If you use synchronization with the starhub option you can even set up more than one board as the trigger master. The boards will be com- bined by a logical OR and therefore the boards will be started if any of the trigger masters has detected a trigger event.

The synchronization OR-trigger is not available when using the cascading option. It is also not available with starhub option prior to hardware version V4. See the initialization section of this manual to find out how to determint the hardware version of the starhub.

If you set up the boards for the synchronization OR trigger all boards that are set as trigger master must be programmed to the same trigger- mode. If the boards are using different trigger modes this will result in a time shift between the boards. It is of course possible to set different edges or different trigger levels on the channels.

It is only possible to use the synchronization OR trigger if the board carrying the starhub piggy-back module is one of the boards that is programmed as a trigger master.

To find out what board is carrying the starhub piggy-back module you make use of the board’s feature registers as described in the chapter about initialising the board.

Example of setting up three boards to be trigger master

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCTRIGGERMASTER);

// Set board 0

to trigger master

SpcSetParam

(hDrv[1],

SPC_COMMAND,

SPC_SYNCTRIGGERMASTER);

// Set

board

1

to

trigger

master

SpcSetParam

(hDrv[2],

SPC_COMMAND,

SPC_SYNCTRIGGERMASTER);

// Set

board

2

to

trigger

master

(5) Define the remaining boards as trigger slaves

As you can set more than one board as the trigger master (starhub option only) you have to tell the driver additionally which of the boards are working as trigger slaves.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_SYNCTRIGGERSLAVE

111

Defines the according board as the trigger slave.

Each of the synchronized boards must be set up either as a trigger master or as a trigger slave to get the synchronization option working correctly. Therefore it does not matter if you use the cascading or starhub option.

It is assumed that only one of the three boards (board 2 in this case) is set up as trigger master, as described in (3)

SpcSetParam

(hDrv[0],

SPC_COMMAND,

SPC_SYNCTRIGGERSLAVE);

//

Setting

all the other boards to

SpcSetParam

(hDrv[1],

SPC_COMMAND,

SPC_SYNCTRIGGERSLAVE);

//

trigger

slave is a must !

 

 

 

 

 

 

 

It sometimes might be necessary to exclude one or more boards from the synchronization trigger. An example for this solution is that one or more output boards are used for continuously generating test patterns, while one or more acqusition boards are triggering for test results or error conditions. Therefore it is possible to exclude a board from the triggerbus so that only a synchronization for clock is done and the ac- cording boards are just using the trigger events they have detected on their own.

Register

Value

Direction

Description

SPC_NOTRIGSYNC

200040

r/w

If activated the dedicated board will use its own trigger modes instead of the synchronization trigger.

 

 

 

 

92

MC.31xx Manual

Page 91 Page 93
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Page 91 Page 93
Contents MC.31xx English version April 27Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Inputs Standard acquisition modesOption Multiple Recording Option Gated SamplingOption Timestamp Option Extra I/OIntroduction PrefaceGeneral Information PrefaceIntroduction Different models of the MC.31xx seriesMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 MC.3112 MC.3122 MC.3132 Additional options Digital inputsExtra I/O Option -XMF Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationIntroductionHardware information Order No DescriptionSystem Requirements Hardware InstallationInstalling the board in the system Hardware Installation Installing a board with digital inputs/outputsInstalling a board with extra I/O Option -XMF Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Installation Software Driver Installation WindowsWindows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Adding boards to the Windows NT driver Software Driver Installation Windows NTWindows NT Linux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software Overview++ Driver Interface Header filesMicrosoft Visual C++ Borland C++ BuilderOther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversSoftware ++ Driver Interface Using the Driver under Linux Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsDelphi Pascal Programming Interface Type definitionInclude Driver ExamplesSoftware VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Installed features and optionsHardware version Date of productionUsed interrupt line Used type of driverProgramming the Board Initialization Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Inputs Channel SelectionImportant note on channels selection Analog InputsChannel rerouting Rerouting information for moduleSPCCHROUTE0 SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeInput termination Automatical adjustment of the offset settingsOverrange bit Spcadjautoadj Adjall Spcadjsave ADJUSER0Standard acquisition modes ProgrammingMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerStarting without interrupt classic mode Command registerMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStatus register Starting with interrupt driven modeStandard acquisition modes Programming Normal mode Fast 8 bit mode201100 Enables the fast 8 bit mode Data organizationStandard mode Reading out the data with SpcGetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming Fifo Mode General InformationBackground Fifo Read Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo acquisition mode Fifo acquisition exampleSpcfifostart SpcfifowaitSample format Standard internal sample rate Clock generationInternally generated sample rate Using plain quartz without PLL Maximum internal sample rate in MS/s normal modeExternal reference clock Clock generationExternal clocking Direct external clockMinimum external sample rate Maximum external samplerate in MS/sFifo External clock with dividerCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Trigger modes and appendant registers General DescriptionSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPulsewidth triggers Positive and negative TTL triggerTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for long LOW pulses TTL pulsewidth trigger for short LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthChannel Trigger Overview of the channel trigger registersSpctriggermode Tmchannel TmchxoffTriggerlevel Spctriggermode TmchorSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffReading out the number of possible trigger levels SPCTRIGGERMODE0 TmchxposSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVDetailed description of the channel trigger modes Channel trigger on positive edgeChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesTmchxposgsp Channel pulsewidth trigger for short positive pulsesChannel pulsewidth trigger for short negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsStandard Mode When using Multiple Recording pretrigger is not availableOption Multiple Recording Recording modesResulting start delays Trigger modesOption Multiple RecordingSpcmemsize SpctriggermodeGeneral information and trigger delay Option Gated SamplingOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelNumber of samples on gate signal Allowed trigger modesOption Gated SamplingTrigger modes External TTL edge triggerExample program Example program Option Gated SamplingChannel trigger Spctriggermode TmttlposStartReset mode Option TimestampTimestamp modes LimitsRefClock mode optional Functions for accessing the dataTimestamp Status Reading out timestamp dataSpctimestampcount Data formatSpcGetData nr, ch, start, len, data Acquisition with Multiple Recording Standard acquisition modeExample programs Option Extra I/O Digital I/OsAnalog Outputs Channel directionProgramming example Programming example Option Extra I/OBit Standard Mode Digital Inputs enabled Option Digital inputsSample format SpcreaddigitalSynchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersLet the master calculate it’s clocking Write Data to on-board memory output boards onlyExample for data writing Define the boards for trigger masterExample of board #2 set as trigger master 4a Define synchronization or triggerDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Restarting the board for another synchronized runExample of Fifo buffer allocation 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixOption Digital inputs Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Pin assignment of the multipin cable
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