Spectrum Brands MC.31XX manual Setup order for the different synchronization options

Page 91

Synchronization (Option)

The setup order for the different synchronization options

 

 

When the boards are synchronized by the option starhub there will be no delay between the connected boards. This is achieved as all boards, including the one the starhub module is mounted on, are connected to the starhub with cables of the same length.

The figure on the right shows the clock of three boards with two channels each that are synchronized by starhub.

The setup order for the different synchronization options

If you setup the boards for the use with synchronization it is important to keep the order within the software commands as mentioned below to get the boards working correctly.

Depending on if you use the board either in standard or in FIFO mode there are slightly different orders in the setup for the synchronization option. The following steps are showing the setups either for standard or FIFO mode.

Setup Order for use with standard (non FIFO) mode and equally clocked boards

(1) Set up the board parameters

Set all parameters like for example sample rate, memsize and trigger modes for all the synchronized boards, except the dedicated registers for the synchronization itself that are shown in the tables below.

All boards must be set to the same settings for the entire clocking registers (see the according chapter for sample rate generation), for the trigger mode and memory and should be set to the same postcounter size to get the same pretrigger sizes as well.

If you use acquisition boards with different pretrigger sizes, please keep in mind that after starting the board the pretrigger memory of all boards will be recorded first, before the boards trigger detection is armed. Take care to prevent boards with a long pretrigger setup time from hangup by adequately checking the board’s status. Long setup times are needed if either you use a huge pretrigger size and/or a slow sample rate.

If you don’t care it might happen that boards with a small pretrigger are armed first and detect a triggerevent, while one or more boards with a huge pretrigger are still not armed. This might lead to an endless waiting-state on these boards, which should be avoided.

Example of board setup for three boards

//--------- Set the Handles to fit for Windows driver ---------

hDrv[0] = 0; hDrv[1] = 1; hDrv[2] = 2;

//(1) ----- Setup all boards, shortened here !!!-----

for (i = 0; i < 3; i++)

 

 

{

1024);

// memory in samples per channel

SpcSetParam (hDrv[i], SPC_MEMSIZE,

SpcSetParam (hDrv[i], SPC_POSTTRIGGER, 512);

// posttrigger in samples

// ...

10000000);

// set sample rate to all boards

SpcSetParam (hDrv[i], SPC_SAMPLERATE,

SpcSetParam (hDrv[i], SPC_TRIGGERMODE, TM_SOFTWARE);

// set trigger mode to all boards

}

 

 

(2) Let the master calculate it’s clocking

To obtain proper clock initailization when doing the first start it is necessary to let the clock master do all clock related calculations prior to setting all the synchronization configuration for the slave boards.

Example of board #0 set as clock master and forced to do the appropriate clock calculation

SpcSetParam (hDrv[0], SPC_COMMAND,

SPC_SYNCCALCMASTER);

// Calculate clock settings on master

 

 

 

(3) Write Data to on-board memory (output boards only)

If one or more of the synchronized boards are used for generating data (arbitrary waveform generator boards or digital I/O boards with one or more channels set to output direction) you have to transfer the data to the board’s on-board memory before starting the synchronization. Please refer to the related chapter for the standard mode in this manual. If none of your synchronized boards is used for generation purposes you can ignore this step.

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard acquisition modes Fifo ModeProgramming the Board Analog InputsOption Extra I/O Option Multiple RecordingOption Gated Sampling Option TimestampPreface IntroductionPreface General InformationMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 Different models of the MC.31xx seriesIntroduction MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMFTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder No Description Dynamic ParametersOrder information IntroductionHardware informationInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsHardware Installation Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Version control InstallationSoftware Driver Installation Windows WindowsDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Windows NT Software Driver Installation Windows NTAdding boards to the Windows NT driver Overview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware Overview SoftwareSoftware Overview First Test with SBenchBorland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParamExamples Delphi Pascal Programming InterfaceType definition Include DriverSoftware Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineDate of production Installed memoryInstalled features and options Hardware versionDriver version Used interrupt lineUsed type of driver Programming the Board InitializationSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeAnalog Inputs Analog InputsChannel Selection Important note on channels selectionSPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetOverrange bit Automatical adjustment of the offset settingsInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallPretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and PosttriggerMinimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamplesStandard acquisition modes Programming Starting with interrupt driven modeStatus register Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit modeValue ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer valueProgramming Speed Limitations Fifo ModeGeneral Information Background Fifo Read60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo acquisition modeFifo acquisition example SpcfifostartSample format Internally generated sample rate Clock generationStandard internal sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clockMaximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rateCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerFifo External TTL trigger Trigger modes and appendant registersGeneral Description Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersTTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulsesSpcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode TmttlhighlpTmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode TmchannelSPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 TmchxoffInput ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short negative pulses Channel pulsewidth trigger for short positive pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsRecording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple RecordingSpctriggermode Resulting start delaysTrigger modesOption Multiple Recording SpcmemsizeSpcgate General information and trigger delayOption Gated Sampling Option Gated SamplingAlignement samples per channel End of gate alignementExternal TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modesSpctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel triggerLimits StartReset modeOption Timestamp Timestamp modesReading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp StatusSpcGetData nr, ch, start, len, data Data formatSpctimestampcount Example programs Standard acquisition modeAcquisition with Multiple Recording Channel direction Option Extra I/ODigital I/Os Analog OutputsProgramming example Option Extra I/O Programming exampleSpcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample formatSynchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger masterArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesRestarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncmasterfifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError Codes Error name Value hex Value dec Error descriptionExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorOption Digital inputs Pin assignment of the multipin cable
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