Spectrum Brands MC.31XX manual Triggerlevel, Spctriggermode Tmchor, SPCTRIGGERMODE0 Tmchxoff

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Trigger modes and appendant registers

Channel Trigger

 

 

If you want to set up a four channel board to detect a triggerevent on either a positive edge on channel1 or a negative edge on channel3 you would have to set up your board as the following example shows.

SpcSetParam (hDrv,

SPC_TRIGGERMODE ,

TM_CHOR );

// Enable channel OR trigger mode

SpcSetParam (hDrv,

SPC_TRIGGERMODE0,

TM_CHXOFF);

// Disable channel0 concerning trigger detection

SpcSetParam (hDrv, SPC_TRIGGERMODE1, TM_CHXPOS);

// Set triggermode of channel1 to positive edge trigger

SpcSetParam (hDrv,

SPC_TRIGGERMODE2,

TM_CHXOFF);

// Disable channel2 concerning trigger detection

SpcSetParam (hDrv, SPC_TRIGGERMODE3, TM_CHXNEG);

// Set triggermode of channel3 to positive edge trigger

SpcSetParam (hDrv, SPC_TRIGGERMODE4,

TM_CHXOFF );

// Disable channel4 concerning trigger detection

SpcSetParam (hDrv, SPC_TRIGGERMODE5,

TM_CHXOFF );

// Disable channel5 concerning trigger detection

SpcSetParam (hDrv, SPC_TRIGGERMODE6,

TM_CHXOFF );

// Disable channel6 concerning trigger detection

SpcSetParam (hDrv, SPC_TRIGGERMODE7,

TM_CHXOFF );

// Disable channel7 concerning trigger detection

Triggerlevel

All of the channel trigger modes listed above require at least one triggerlevel to be set (except TM_CHXOFF of course). Some like the window trigger require even two levels (upper and lower level) to be set. Before explaining the different channel trigger modes, it is necessary to explain the board’s series specific range of triggerlevels.

After the data has been sampled, the upper N data bits are compared with the N bits of the trigger levels. The amount of bits, the trigger levels are represented with depends on the board’s series. The following table shows the level registers and the possible values they can be set to for your specific board.

8 bit resolution for the trigger levels:

Register

Value

Direction

Description

Range

SPC_HIGHLEVEL0

42000

r/w

Defines the upper level (triggerlevel) for channel 0

-127 to +127

 

 

 

 

 

SPC_HIGHLEVEL1

42001

r/w

Defines the upper level (triggerlevel) for channel 1

-127 to +127

 

 

 

 

 

SPC_HIGHLEVEL2

42002

r/w

Defines the upper level (triggerlevel) for channel 2

-127 to +127

SPC_HIGHLEVEL3

42003

r/w

Defines the upper level (triggerlevel) for channel 3

-127 to +127

 

 

 

 

 

SPC_HIGHLEVEL4

42004

r/w

Defines the upper level (triggerlevel) for channel 4

-127 to +127

 

 

 

 

 

SPC_HIGHLEVEL5

42005

r/w

Defines the upper level (triggerlevel) for channel 5

-127 to +127

SPC_HIGHLEVEL6

42006

r/w

Defines the upper level (triggerlevel) for channel 6

-127 to +127

SPC_HIGHLEVEL7

42007

r/w

Defines the upper level (triggerlevel) for channel 7

-127 to +127

 

 

 

 

 

SPC_LOWLEVEL0

42100

r/w

Defines the lower level (triggerlevel) for channel 0

-127 to +127

SPC_LOWLEVEL1

42101

r/w

Defines the lower level (triggerlevel) for channel 1

-127 to +127

SPC_LOWLEVEL2

42102

r/w

Defines the lower level (triggerlevel) for channel 2

-127 to +127

 

 

 

 

 

SPC_LOWLEVEL3

42103

r/w

Defines the lower level (triggerlevel) for channel 3

-127 to +127

SPC_LOWLEVEL4

42104

r/w

Defines the lower level (triggerlevel) for channel 4

-127 to +127

SPC_LOWLEVEL5

42105

r/w

Defines the lower level (triggerlevel) for channel 5

-127 to +127

 

 

 

 

 

SPC_LOWLEVEL6

42106

r/w

Defines the lower level (triggerlevel) for channel 6

-127 to +127

SPC_LOWLEVEL7

42107

r/w

Defines the lower level (triggerlevel) for channel 7

-127 to +127

In the above table the values for the triggerlevels represent the digital values for the corresponding data width N of the triggerlevels. If for example the triggerlevels are represented by 8 bit, the bipolar range would be -128 … 127. To archieve symmetric triggerlevels the most negative value is not used and the so resulting range would be -127 … +127.

As the triggerlevels are compared to the digitized data, the triggerlevels depend on the channels input range. For every input range available to your board there is a corresponding range of triggerlevels. On the different input ranges the possible stepsize for the triggerlevels differs as well as the maximum and minimum values. The following table, gives you the absolute triggerlevels for your specific board’s series.

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard acquisition modes Fifo ModeProgramming the Board Analog InputsOption Extra I/O Option Multiple RecordingOption Gated Sampling Option TimestampPreface IntroductionPreface General InformationMC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 Different models of the MC.31xx seriesIntroduction MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMFTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder No Description Dynamic ParametersOrder information IntroductionHardware informationInstalling the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsHardware Installation Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Version control InstallationSoftware Driver Installation Windows WindowsDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Windows NT Software Driver Installation Windows NTAdding boards to the Windows NT driver Overview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware Overview SoftwareSoftware Overview First Test with SBenchBorland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParamExamples Delphi Pascal Programming InterfaceType definition Include DriverSoftware Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineDate of production Installed memoryInstalled features and options Hardware versionDriver version Used interrupt lineUsed type of driver Programming the Board InitializationSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeAnalog Inputs Analog InputsChannel Selection Important note on channels selectionSPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetOverrange bit Automatical adjustment of the offset settingsInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallPretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and PosttriggerMinimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamplesStandard acquisition modes Programming Starting with interrupt driven modeStatus register Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit modeValue ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer valueProgramming Speed Limitations Fifo ModeGeneral Information Background Fifo Read60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo acquisition modeFifo acquisition example SpcfifostartSample format Internally generated sample rate Clock generationStandard internal sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clockMaximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rateCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerFifo External TTL trigger Trigger modes and appendant registersGeneral Description Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersTTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulsesSpcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode TmttlhighlpTmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode TmchannelSPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 TmchxoffInput ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short negative pulses Channel pulsewidth trigger for short positive pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsRecording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple RecordingSpctriggermode Resulting start delaysTrigger modesOption Multiple Recording SpcmemsizeSpcgate General information and trigger delayOption Gated Sampling Option Gated SamplingAlignement samples per channel End of gate alignementExternal TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modesSpctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel triggerLimits StartReset modeOption Timestamp Timestamp modesReading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp StatusSpcGetData nr, ch, start, len, data Data formatSpctimestampcount Example programs Standard acquisition modeAcquisition with Multiple Recording Channel direction Option Extra I/ODigital I/Os Analog OutputsProgramming example Option Extra I/O Programming exampleSpcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample formatSynchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger masterArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesRestarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncmasterfifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError Codes Error name Value hex Value dec Error descriptionExtra I/O with external connectorOption -XMF Pin assignment of the multipin connectorOption Digital inputs Pin assignment of the multipin cable
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