Spectrum Brands MC.31XX manual Synchronization Option, Different synchronization options

Page 90

The different synchronization options

Synchronization (Option)

 

 

Synchronization (Option)

This option allows the connection of multiple boards to generate a multi-channel system. It is possible to synchronize multiple Spectrum boards of the same type as well as different board types. Therefore the synchronized boards must be linked concerning the board’s system clock and the trigger signals.

If no synchronization is desired for a certain board you can exclude it by setting the register shown in the following table. This must be done seperately for every board that should not work synchronized.

Register

Value

Direction

Description

SPC_COMMAND

0

r/w

Command register of the board

 

SPC_NOSYNC

120

Disables the synchronization globally.

The different synchronization options

Synchronization with option cascading

With the option cascading up to four Spectrum boards can be synchronized. All boards are connected with one synchronization cable on their sync-connectors (for details please refer to the chapter about installing the hardware).

As the synchronization lines are organized as a bus topology, there is a need for termination at both ends of the bus. This is done in factory for the both end-boards. The maximum possible two middle-boards have no termination on board.

When synchronizing multiple boards, one is set to be the clock master for all the connected boards. All the other boards are working as clock slaves. It’s also possible to temporarily disable boards from the synchronization.

The same board or another one of the connected boards can be defined as a trigger master for all boards. All trigger modes of the trigger master board can be used. It is also possible to synchronize the connected boards only for the samplerate and not for trigger. This can be useful if one generator board is continuously generating a test- pattern, while the connected acquisition board is triggering for test results or error conditions of the device under test.

For the fact that the termination is set in factory the order of the syncronized boards cannot be changed by the user. Please refer to the boards type plate for details on the board’s termination. End boards are marked with the option „cs-end“ while middle boards are marked with the option „cs-mid“

When the boards are synchronized by the option cascading there will be a delay of about 500 ps between two adjacent boards.

The figure on the right shows the clocks of three cascaded boards with two channels each, where one end-board is de- fined as a clock master. Slave 1 is therefore a middle-board and Slave 2 is the other end-board. The resulting delay be- tween data of the two end-boards is therefore about 1 ns.

Please keep in mind that the delay between the channels of two boards is depending on which board is actually set up as the clock master and what boards are directly adjacent to the master.

Synchronization with option starhub

With the option starhub up to 16 Spectrum boards can be synchronized. All boards are connected with a seperate synchronization cable from their sync-connectors to the starhub module, which is a piggy-back module on one Spectrum board (for details please refer to the chapter about installing the hardware).

When synchronizing multiple boards, one is set to be the clock master for all the connected boards. All the other boards are working as clock slaves. It’s also possible to temporarily disable the synchronization of one board. This board then runs individually while the other boards still are synchronized.

The same board or another one of the connected boards can be defined as a trigger master for all boards. All trigger modes of the board defined as the trigger master can be used. It is also possible to synchronize the connected boards only for the samplerate and not for trigger. This can be useful, if one generator board is continuously generating a testpattern, while the connected acquisition board is triggering for test results or error conditions of the device under test.

Additionally you can even define more than one board as a trigger master. The trigger events of all boards are combined by a logical OR, so that the first board that detects a trigger will start the boards. This OR connection is available starting with starhub hardware version V4.

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MC.31xx Manual

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Contents MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation SoftwareAnalog Inputs Fifo ModeProgramming the Board Standard acquisition modesOption Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/OGeneral Information IntroductionPreface PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationIntroductionHardware information Dynamic ParametersOrder information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux OverviewDriver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driverFirst Test with SBench SoftwareSoftware Overview Software OverviewMicrosoft Visual C++ ++ Driver InterfaceHeader files Borland C++ BuilderDriver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include DriversFunction SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData WindowsInclude Driver Delphi Pascal Programming InterfaceType definition ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tablesStarting the automatic initialization routine Example for error checkingInitialization PCI RegisterHardware version Installed memoryInstalled features and options Date of productionProgramming the Board Initialization Used interrupt lineUsed type of driver Driver versionSpcpcimemsize Powerdown and resetExample program for the board initialization SpcpciserialnoImportant note on channels selection Analog InputsChannel Selection Analog InputsSPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttriggerMaximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organizationValue ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer valueProgramming Background Fifo Read Fifo ModeGeneral Information Speed LimitationsTheoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffersAnalog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boardsSpcfifostart Example Fifo acquisition modeFifo acquisition example SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generationMinimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Software trigger Trigger modes and appendant registersGeneral Description External TTL triggerTrigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL triggerTTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulsesSpctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses SpcpulsewidthSpctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers TmchxoffSPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 TmchxoffSPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVChannel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsOption Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modesSpcmemsize Resulting start delaysTrigger modesOption Multiple Recording SpctriggermodeOption Gated Sampling General information and trigger delayOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelOption Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge triggerChannel trigger Example programExample program Option Gated Sampling Spctriggermode TmttlposTimestamp modes StartReset modeOption Timestamp LimitsTimestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Analog Outputs Option Extra I/ODigital I/Os Channel directionProgramming example Programming example Option Extra I/OSample format Bit Standard Mode Digital Inputs enabledOption Digital inputs SpcreaddigitalSynchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhubLet the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards onlyExample of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or triggerDefine the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronizationRead data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized runSpcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample ratesError name Value hex Value dec Error description Error CodesError Codes AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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