Spectrum Brands MC.31XX Timestamp Status, Reading out timestamp data, RefClock mode optional

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Timestamp Status

Option Timestamp

 

 

TS_MODE_STARTRESET

11

Must be written to enable the StartReset timestamp mode. The counter is reset on each start of the board. The times- tamps values are relative to the board start.

RefClock mode (optional)

The counter is split in a HIGH and a LOW part and an additional seconds signal, that affects both parts of the counter (TTL pulse with f = 1 Hz) must be fed in externally.

The HIGH part counts the seconds that have elapsed since the last counter reset with the reset command TS_RESET. The LOW part is reset to zero on every seconds signal and is clocked with the actual sample rate. The edge of the external secondssignal must be set seperately as described below.

This mode allows the recording of an absolute time of a trigger event. This even allows the synchronization of data that has been recorded with different boards.

Register

Value

Direction

Description

SPC_TIMESTAMP_CMD

47000

w

Writes a command to the timestamp command register.

SPC_TIMESTAMP_CMD

47000

r

Reads out the actual timestamp mode.

 

TS_RESET

0

Resets the whole counter of the timestamp module to zero. Waits for synchronization to an external seconds signal.

 

 

 

This may last up to 1 second. The lower part of the counter can be reset with the external fed in second signal. The

 

 

 

edge of the reset signal can be programmed with the SPC_TIMESTAMP_RESETMODE register as shown in the table

 

 

 

below.

 

 

TS_MODE_DISABLE

10

Disables the timestamp module. No timestamps are recorded.

 

TS_MODE_REFCLOCK

13

Must be written to enable the RefClock timestamp mode. The counter must be manually reset by writing the command

 

 

 

TS_RESET to the command register. The counter is splitted into two parts. The upper part counts the seconds of an

 

 

 

external reference clock. The lower part is reset on each second signal and counts the samples.

The edge of the external TTL seconds signal can be programmed by the following register either to detect the rising or falling edge.

Register

Value

Direction

Description

SPC_TIMESTAMP_RESETMODE

47050

r/w

Defines the active edge of the external fed in seconds signal to reset the lower part of the counter. The

 

 

 

 

values written here do not affect the timestamp command TS_RESET.

 

TS_RESET_POS

10

The lower part of the counter will be reset on every rising edge of the external reset signal (seconds signal).

 

 

 

 

 

TS_RESET_NEG

20

The lower part of the counter will be reset on every falling edge of the external reset signal (seconds signal).

To get recordings in relation to each other it is importent to know the absolute start time. This time can be easily read out by the following register. The time is given back in seconds since midnight (00:00:00), January 1, 1970, which is the standard ’time_t’ in C/C++.

Register

Value

Direction

Description

SPC_TIMESTAMP_STARTTIME

47030

r

Reads out the start time of the RefClock mode. Return value is the number of seconds since midnight

 

 

 

(00:00:00), January 1, 1970, which is the standard ’time_t’ in C/C++.

Timestamp Status

The timestamp module has its own status register for the timestamp FIFO. You can easily read out the FIFO status with the help of the timestamp status register shown in the table below.

Register

Value

Direction

Description

SPC_TIMESTAMP_STATUS

47010

r

Reads the status of the timestamp FIFO.

 

TS_FIFO_EMPTY

0

The timestamp FIFO is still empty.

 

 

 

 

 

TS_FIFO_LESSHALF

1

There are values in the timestamp FIFO but less than half of the FIFO is filled.

 

TS_FIFO_MOREHALF

2

More than half of the FIFO is filled with timestamps.

 

TS_FIFO_OVERFLOW

3

The timestamp FIFO is full and possibly data has been lost.

Reading out timestamp data

Functions for accessing the data

There are two possibilities to access the timestamps that have been stored in the timestamp FIFO.

Reading out a single timestamp

You can read out one 32 bit value from the timestamp FIFO by using the register shown in the table below.

Register

Value

Direction

Description

SPC_TIMESTAMP_FIFO

47040

r

Get one 32 bit value from the timestamp FIFO. If the FIFO is empty a zero will be returned.

Because accessing the timestamp with this function will be done with single accesses, getting the value(s) this way is much slower than using the SpcGetData function as described below.

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MC.31xx Manual

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Contents MC.31xx English version April 27Page Hardware Installation Software Driver InstallationIntroduction SoftwareFifo Mode Programming the BoardAnalog Inputs Standard acquisition modesOption Multiple Recording Option Gated SamplingOption Timestamp Option Extra I/OIntroduction PrefaceGeneral Information PrefaceDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Additional options Digital inputsExtra I/O Option -XMF Introduction Additional optionsStarhub TimestampSpectrum type plate Block diagram Technical Data Hardware informationDynamic Parameters Order informationIntroductionHardware information Order No DescriptionHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cablesInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Installation Software Driver Installation WindowsWindows Version controlDriver Update Windows Driver Update Software Driver Installation Windows XPWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux OverviewInstalling the device Now it is possible to access the board using this deviceDriver info Automatic load of the driverSoftware Software OverviewFirst Test with SBench Software Overview++ Driver Interface Header filesMicrosoft Visual C++ Borland C++ BuilderOther Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include DriversSoftware ++ Driver Interface Using the Driver under Linux Function SpcSetParamFunction SpcSetParam Function SpcSetData WindowsDelphi Pascal Programming Interface Type definitionInclude Driver ExamplesSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tablesExample for error checking InitializationStarting the automatic initialization routine PCI RegisterInstalled memory Installed features and optionsHardware version Date of productionUsed interrupt line Used type of driverProgramming the Board Initialization Driver versionPowerdown and reset Example program for the board initializationSpcpcimemsize SpcpciserialnoAnalog Inputs Channel SelectionImportant note on channels selection Analog InputsChannel rerouting Rerouting information for moduleSPCCHROUTE0 SPCCHROUTE1Setting up the inputs Input rangesInput offset Register Value Direction Description Offset rangeAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0Standard acquisition modes ProgrammingMemory, Pre- and Posttrigger Pretrigger = memsize posttriggerStarting without interrupt classic mode Command registerMaximum posttrigger in MSamples Minimum memsize and posttrigger in samplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Normal mode Fast 8 bit mode201100 Enables the fast 8 bit mode Data organizationStandard mode Reading out the data with SpcGetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer valueProgramming Fifo Mode General InformationBackground Fifo Read Speed LimitationsProgramming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffersFifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boardsExample Fifo acquisition mode Fifo acquisition exampleSpcfifostart SpcfifowaitSample format Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz without PLL Maximum internal sample rate in MS/s normal modeExternal reference clock Clock generationExternal clocking Direct external clockMinimum external sample rate Maximum external samplerate in MS/sExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Trigger modes and appendant registers General DescriptionSoftware trigger External TTL triggerExample on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL triggerPulsewidth triggers Positive and negative TTL triggerTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulsesTTL pulsewidth trigger for long LOW pulses TTL pulsewidth trigger for short LOW pulsesSpctriggermode Tmttlhighlp SpcpulsewidthChannel Trigger Overview of the channel trigger registersSpctriggermode Tmchannel TmchxoffTriggerlevel Spctriggermode TmchorSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 TmchxoffReading out the number of possible trigger levels SPCTRIGGERMODE0 TmchxposSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mVDetailed description of the channel trigger modes Channel trigger on positive edgeChannel trigger on negative edge Channel trigger on positive and negative edgeChannel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulsesChannel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulsesChannel window trigger for entering signals Channel window trigger for leaving signalsChannel window trigger for long inner signals Channel window trigger for long outer signalsChannel window trigger for short inner signals Channel window trigger for short outer signalsStandard Mode When using Multiple Recording pretrigger is not availableOption Multiple Recording Recording modesResulting start delays Trigger modesOption Multiple RecordingSpcmemsize SpctriggermodeGeneral information and trigger delay Option Gated SamplingOption Gated Sampling SpcgateEnd of gate alignement Alignement samples per channelNumber of samples on gate signal Allowed trigger modesOption Gated SamplingTrigger modes External TTL edge triggerExample program Example program Option Gated SamplingChannel trigger Spctriggermode TmttlposStartReset mode Option TimestampTimestamp modes LimitsRefClock mode optional Functions for accessing the dataTimestamp Status Reading out timestamp dataData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Option Extra I/O Digital I/OsAnalog Outputs Channel directionProgramming example Programming example Option Extra I/OBit Standard Mode Digital Inputs enabled Option Digital inputsSample format SpcreaddigitalSynchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhubSetup order for the different synchronization options Set up the board parametersLet the master calculate it’s clocking Write Data to on-board memory output boards onlyExample for data writing Define the boards for trigger masterExample of board #2 set as trigger master 4a Define synchronization or triggerDefine the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronizationStart all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Restarting the board for another synchronized runExample of Fifo buffer allocation 2a Write first data for output boardsSpcsyncmasterfifo SpcsyncslavefifoAdditions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xxSetting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample ratesError Codes Error CodesError name Value hex Value dec Error description AppendixPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable