Spectrum Brands MC.31XX manual Option Extra I/O, Digital I/Os, Analog Outputs, Channel direction

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Option Extra I/O

Digital I/Os

 

 

Option Extra I/O

Digital I/Os

With this simple-to-use enhancement it is possible to control a wide range of external instruments or other equipment. Therefore you have several digital I/Os and the 4 analog outputs available. All extra I/O lines are completely independent from the board’s function, data di- rection or sample rate and directly controlled by software (asynchronous I/Os).

The extra I/O option is useful if an external amplifier should be controlled, any kind of signal source must be programmed, an antenna must be adjusted, a status information from external machine has to be obtained or different test signals have to be routed to the board.

It is not possible to use this option together with the star hub or timestamp option, because there is just space for one piggyback module on the on-board expansion slot.

Channel direction

Option -XMF (external connector)

The additional inputs and outputs are mounted on an extra bracket.

The direction of the 24 available digital lines can be programmed for every group of eight lines. The table below shows the direction register and the possible values. To combine the values so simply have to OR them bitwise.

Register

Value

Direction

Description

 

SPC_XIO_DIRECTION

47100

r/w

Defines bytewise the direction of the digital I/O lines. The values can be combined by a bitwise OR.

 

XD_CH0_INPUT

0

Sets the direction of channel 0 (bit D7…D0) to input.

 

 

 

 

 

XD_CH1_INPUT

0

Sets the direction of channel 1 (bit D15…D8) to input.

 

 

 

 

 

XD_CH2_INPUT

0

Sets the direction of channel 2 (bit D23…D16) to input.

 

XD_CH0_OUTPUT

1

Sets the direction of channel 0 (bit D7…D0) to output.

 

 

 

 

 

 

XD_CH1_OUTPUT

2

Sets the direction of channel 1

(bit D15…D8) to output.

 

 

 

 

 

 

XD_CH2_OUTPUT

4

Sets the direction of channel 2

(bit D23…D16) to output.

Transfer Data

The outputs can be written or read by a single 32 bit register. If the register is read, the actual pin data will be taken. Therefore reading the data of outputs gives back the generated pattern. The single bits of the digital I/O lines correspond with the bitnumber of the 32 bit register. Values written to the most significant byte will be ignored.

Register

Value

Direction

Description

SPC_XIO_DIGITALIO

47110

r

Reads the data directly from the pins of all digital I/O lines either if they are declared as inputs or

 

 

 

outputs.

SPC_XIO_DIGITALIO

47110

w

Writes the data to all digital I/O lines that are declared as outputs. Bytes that are declared as inputs

 

 

 

will ignore the written data.

Analog Outputs

In addition to the digital I/Os there are four analog outputs available. These outputs are directly programmed with the voltage values in mV. As the analog outputs are driven by a 12 bit DAC, the output voltage can be set in a stepsize of 5 mV. The table below shows the registers, you must write the desired levels too. If you read these outputs, the actual output level is given back from an internal software register.

Register

Value

Direction

Description

Offset range

SPC_XIO_ANALOGOUT0

47120

r/w

Defines the output value for the analog output A0.

± 10000 mV in steps of 5 mV

 

 

 

 

 

SPC_XIO_ANALOGOUT1

47121

r/w

Defines the output value for the analog output A1.

± 10000 mV in steps of 5 mV

SPC_XIO_ANALOGOUT2

47122

r/w

Defines the output value for the analog output A2.

± 10000 mV in steps of 5 mV

SPC_XIO_ANALOGOUT3

47123

r/w

Defines the output value for the analog output A3.

± 10000 mV in steps of 5 mV

After programming the levels of all analog outputs by the registers above, you have to update the analog outputs. This is done by the register shown in the table below. To update all of the outputs all you need to do is write a “1“ to the dedicated register.

Register

Value

Direction

Description

SPC_XIO_WRITEDACS

47130

w

All the analog outputs are simultaniously updated by the programmed levels if a “1“ is written.

(c) Spectrum GmbH

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Contents English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation IntroductionStandard acquisition modes Fifo ModeProgramming the Board Analog InputsOption Extra I/O Option Multiple RecordingOption Gated Sampling Option TimestampPreface IntroductionPreface General InformationDifferent models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMFTimestamp StarhubSpectrum type plate Hardware information Block diagram Technical DataOrder No Description Dynamic ParametersOrder information IntroductionHardware informationHardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boardsInstalling multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Version control InstallationSoftware Driver Installation Windows WindowsDriver Update Windows Driver Update Windows XP Software Driver InstallationWindows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Overview LinuxAutomatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver infoSoftware Overview SoftwareSoftware Overview First Test with SBenchBorland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functionsFunction SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParamExamples Delphi Pascal Programming InterfaceType definition Include DriverSoftware Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board OverviewPCI Register Example for error checkingInitialization Starting the automatic initialization routineDate of production Installed memoryInstalled features and options Hardware versionDriver version Used interrupt lineUsed type of driver Programming the Board InitializationSpcpciserialno Powerdown and resetExample program for the board initialization SpcpcimemsizeAnalog Inputs Analog InputsChannel Selection Important note on channels selectionSPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0Input ranges Setting up the inputsRegister Value Direction Description Offset range Input offsetAutomatical adjustment of the offset settings Overrange bitInput termination Spcadjsave ADJUSER0 Spcadjautoadj AdjallPretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and PosttriggerMinimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamplesStarting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit modeValue ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer valueProgramming Speed Limitations Fifo ModeGeneral Information Background Fifo Read60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus ThroughputDigital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boardsSpcfifowait Example Fifo acquisition modeFifo acquisition example SpcfifostartSample format Clock generation Internally generated sample rateStandard internal sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clockMaximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rateExternal clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo External TTL trigger Trigger modes and appendant registersGeneral Description Software triggerPositive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registersTTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulsesSpcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode TmttlhighlpTmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode TmchannelSPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 TmchxoffInput ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edgeChannel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulsesChannel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulsesChannel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulsesChannel window trigger for leaving signals Channel window trigger for entering signalsChannel window trigger for long outer signals Channel window trigger for long inner signalsChannel window trigger for short outer signals Channel window trigger for short inner signalsRecording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple RecordingSpctriggermode Resulting start delaysTrigger modesOption Multiple Recording SpcmemsizeSpcgate General information and trigger delayOption Gated Sampling Option Gated SamplingAlignement samples per channel End of gate alignementExternal TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modesSpctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel triggerLimits StartReset modeOption Timestamp Timestamp modesReading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp StatusData format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Channel direction Option Extra I/ODigital I/Os Analog OutputsProgramming example Option Extra I/O Programming exampleSpcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample formatSynchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascadingWrite Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger masterArm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slavesRestarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards onlySpcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards SpcsyncmasterfifoGeneral information Additions for synchronizing different boards20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividersBoard type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/sAdditions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo modeAppendix Error CodesError Codes Error name Value hex Value dec Error descriptionPin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable
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