Xilinx manual ML605 Evaluation Board ML605 Features Cont’d, Sgmii, WDW6TP

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Chapter 1: ML605 Evaluation Board

Table 1-1:		ML605 Features (Cont’d)

Number		Feature	Notes	Schematic
Number		Feature	Notes	Page
				Page

		Clock generation	200 MHz OSC, oscillator socket, SMA	30
		Clock generation	connectors	30
			connectors

		a. 200 MHz oscillator (on	Epson 200 MHz 2.5V LVDS OSC	30
		backside)	Epson 200 MHz 2.5V LVDS OSC	30
		backside)
7
7		b. Oscillator socket, single-	MMD Components 66 MHz 2.5V	30
		ended

		c. SMA connectors	SMA pair	30

		d. MGT REFCLK SMA	SMA pair	30
		connectors	SMA pair	30
		connectors

8		GTX RX/TX port	SMA x4	30

9		PCIe Gen1 (8-lane),	Card edge connector, 8-lane	21
9		Gen2 (4-lane)	Card edge connector, 8-lane	21
		Gen2 (4-lane)

10		SFP connector and cage	AMP 136073-1	23

11		Ethernet (10/100/1000) with	Marvell M88E1111 EPHY	24
11		SGMII	Marvell M88E1111 EPHY	24
		SGMII

12		USB Mini-B, USB-to-UART	Silicon Labs CP2103GM bridge	33
12		bridge	Silicon Labs CP2103GM bridge	33
		bridge

13		USB-A Host, USB Mini-B	Cypress CY7C67300-100AXI	27
13		peripheral connectors	controller	27
		peripheral connectors	controller

14		Video - DVI connector	Chrontel CH7301C-TF Video codec	28, 29

15		IIC NV EEPROM, 8 Kb	ST Microelectronics M24C08-	32
15		(on backside)	WDW6TP	32
		(on backside)	WDW6TP

		Status LEDs		13, 24, 31

		a. Ethernet status	Right-angle link rate and direction	24
16			LEDs	24
			LEDs

		b. FPGA INIT, DONE	Init (red), Done (green)	31

		c. System ACE CF status	Status (green), Error (red)	13

		User I/O		31

		a. User LEDs, green (8)	User I/O (active-High)	30, 31, 33

		b. User pushbuttons, N.O.	User I/O (active-High)	31
		momentary (5)	User I/O (active-High)	31
		momentary (5)

17		c. User LEDs, green (5)	User I/O (active-High)	31
17
		d. User DIP switch (8-pole)	User I/O (active-High)	31

		e. User GPIO SMA	SMA pair	30
		connectors	SMA pair	30
		connectors

		f. LCD 16 character x 2 line	Displaytech S162D BA BC	33
		display	Displaytech S162D BA BC	33
		display

12	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch PinUser SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References