Xilinx ML605 manual Multi-Gigabit Transceivers GTX MGTs, Ics

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Detailed Description

8. Multi-Gigabit Transceivers (GTX MGTs)

The ML605 provides access to 20 MGTs.

•Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers

•Eight (8) of the MGTs are wired to the FMC HPC connector (J64)

•One (1) MGT is wired to SMA connectors (J26, J27)

•One (1) MGTs is wired to the FMC LPC connector (J63)

•One (1) MGT is wired to the SFP Module connector (P4)

•One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)

Note: xxxMHz = user specified frequency

GTX_X0Y19 GTX_X0Y18

116

SGMII

SMA

100 MHz in from PCIe Fingers

(HCSL)

ICS

854104

SGMII 125 MHz LVDS

SMA xxx MHz LVDS

FMC#2 LPC xxxMHz GBTCLK0 LVDS

AC coupling on Mezz

100 MHz LVDS

250 MHz LVDS

ICS874001

REFCLK0

REFCLK1

GTX_X0Y17 GTX_X0Y16

GTX_X0Y15 GTX_X0Y14

REFCLK0

REFCLK1

GTX_X0Y13 GTX_X0Y12

GTX_X0Y11 GTX_X0Y10

BANK_115 BANK_

SFP

FMC#2

PCIe Lane1 PCIe Lane 2

PCIe Lane 3 PCIe Lane 4

PCIe Lane 5

PCIe Lane 6

PCIe

No Connect

No Connect

No Connect

REFCLK0

REFCLK1

GTX_X0Y09

GTX_X0Y08

BANK_114

PCIe Lane 7

PCIe Lane 8

FMC#1 HPC xxx MHz LVDS GBTCLK0 AC coupling on Mezz

(LVDS)

FMC#1 HPC CLK2_M2C

	(LVDS)		ICS
	(LVDS)		854104

To FPGA CLK2_M2C_IO CC pin

FMC#1 HPC xxx MHz LVDS GBTCLK1 AC coupling on Mezz

(LVDS)

FMC#1 HPC CLK3_M2C

	(LVDS)		ICS
	(LVDS)		854104

To FPGA CLK3_M2C_IO CC pin

GTX_X0Y07 GTX_X0Y06

REFCLK0

REFCLK1

GTX_X0Y05 GTX_X0Y04

GTX_X0Y03 GTX_X0Y02

REFCLK0

REFCLK1

GTX_X0Y01

GTX_X0Y00

BANK_112 BANK_113

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

PCIe

UG534_10_101409

Figure 1-10: MGT Clocking

References

See the Virtex-6 FPGA GTX Transceivers User Guide. [Ref 12]

ML605 Hardware User Guide	www.xilinx.com	31
UG534 (v1.2.1) January 21, 2010

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Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardIIC Eeprom 1 KB FeaturesML605 Evaluation Board SMAFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramDDR3 Sodimm ML605 FeaturesFeature Detailed DescriptionSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration3Voltage Rails U1 Fpga Bank 2Virtex-6 Fpga Configuration Modes M20Voltage Rails Cclk Direction4DDR3 Sodimm Connections MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank VCC1V5FPGADDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD3 DQ3 FLASHD0 DQ0FLASHD1 DQ1 FLASHD2 DQ2Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections GTXE1X0Y6 AA3 PCIERX7PAA4 PCIERX7N PCIE100MMGT0PSFP Module Connector Bit2 Bit1 Bit0 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYU80 M88E1111 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation 13Ethernet PHYConnections U1 Fpga PinRXD5 PHYRXD4RXD4 PHYRXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpgainitb User I/OFpga Init and Done LEDs Controlled LEDUser LEDs 18User LEDs and Gpio Connector, Directional LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUsersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08N FMCHPCHB09NFMCHPCHB08P FMCHPCHB13PDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFBM2C VadjVIOBM2C Vadj VREFAM2C VadjVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationUCD7230RGWR UCD9240PFCVccintfpga Vccaux29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References