Xilinx ML605 manual NET PCIERX2N

Page 88

Appendix C: ML605 Master UCF

NET "PCIE_RX2_N"

LOC = "L4";

## B24

on P1

NET "PCIE_RX2_P"

LOC = "L3";

## B23

on P1

NET "PCIE_RX3_N"

LOC = "N4";

## B28

on P1

NET "PCIE_RX3_P"

LOC = "N3";

## B27

on P1

NET "PCIE_RX4_N"

LOC = "R4";

## B34

on P1

NET "PCIE_RX4_P"

LOC = "R3";

## B33

on P1

NET "PCIE_RX5_N"

LOC = "U4";

## B38

on P1

NET "PCIE_RX5_P"

LOC = "U3";

## B37

on P1

NET "PCIE_RX6_N"

LOC = "W4";

## B42

on P1

NET "PCIE_RX6_P"

LOC = "W3";

## B41

on P1

NET "PCIE_RX7_N"

LOC = "AA4";

## B46

on P1

NET "PCIE_RX7_P"

LOC = "AA3";

## B45

on P1

NET "PCIE_TX0_N"

LOC = "F2";

## A17

on P1

NET "PCIE_TX0_P"

LOC = "F1";

## A16

on P1

NET "PCIE_TX1_N"

LOC = "H2";

## A22

on P1

NET "PCIE_TX1_P"

LOC = "H1";

## A21

on P1

NET "PCIE_TX2_N"

LOC = "K2";

## A26

on P1

NET "PCIE_TX2_P"

LOC = "K1";

## A25

on P1

NET "PCIE_TX3_N"

LOC = "M2";

## A30

on P1

NET "PCIE_TX3_P"

LOC = "M1";

## A29

on P1

NET "PCIE_TX4_N"

LOC = "P2";

## A36

on P1

NET "PCIE_TX4_P"

LOC = "P1";

## A35

on P1

NET "PCIE_TX5_N"

LOC = "T2";

## A40

on P1

NET "PCIE_TX5_P"

LOC = "T1";

## A39

on P1

NET "PCIE_TX6_N"

LOC = "V2";

## A44

on P1

NET "PCIE_TX6_P"

LOC = "V1";

## A43

on P1

NET "PCIE_TX7_N"

LOC = "Y2";

## A48

on P1

NET "PCIE_TX7_P"

LOC = "Y1";

## A47

on P1

NET "PCIE_WAKE_B_LS"

LOC = "AD22";

## B11

on P1

##

 

 

 

NET "PHY_COL"

LOC = "AK13";

## 114

on U80

NET "PHY_CRS"

LOC = "AL13";

## 115

on U80

NET "PHY_INT"

LOC = "AH14";

## 32

on U80

NET "PHY_MDC"

LOC = "AP14";

## 35

on U80

NET "PHY_MDIO"

LOC = "AN14";

## 33

on U80

NET "PHY_RESET"

LOC = "AH13";

## 36

on U80

NET "PHY_RXCLK"

LOC = "AP11";

## 7

on U80

NET "PHY_RXCTL_RXDV"

LOC = "AM13";

## 4

on U80

NET "PHY_RXD0"

LOC = "AN13";

## 3

on U80

NET "PHY_RXD1"

LOC = "AF14";

## 128

on U80

NET "PHY_RXD2"

LOC = "AE14";

## 126

on U80

NET "PHY_RXD3"

LOC = "AN12";

## 125

on U80

NET "PHY_RXD4"

LOC = "AM12";

## 124

on U80

NET "PHY_RXD5"

LOC = "AD11";

## 123

on U80

NET "PHY_RXD6"

LOC = "AC12";

## 121

on U80

NET "PHY_RXD7"

LOC = "AC13";

## 120

on U80

NET "PHY_RXER"

LOC = "AG12";

## 9

on U80

NET "PHY_TXCLK"

LOC = "AD12";

## 10

on U80

NET "PHY_TXCTL_TXEN"

LOC = "AJ10";

## 16

on U80

NET "PHY_TXC_GTXCLK"

LOC = "AH12";

## 14

on U80

NET "PHY_TXD0"

LOC = "AM11";

## 18

on U80

NET "PHY_TXD1"

LOC = "AL11";

## 19

on U80

NET "PHY_TXD2"

LOC = "AG10";

## 20

on U80

NET "PHY_TXD3"

LOC = "AG11";

## 24

on U80

NET "PHY_TXD4"

LOC = "AL10";

## 25

on U80

NET "PHY_TXD5"

LOC = "AM10";

## 26

on U80

NET "PHY_TXD6"

LOC = "AE11";

## 28

on U80

NET "PHY_TXD7"

LOC = "AF11";

## 29

on U80

NET "PHY_TXER"

LOC = "AH10";

## 13

on U80

##

 

 

 

## NET "PLATFLASH_L_B"

LOC = "AC23";

## SEE

NET "FLASH_NN" GROUP

##

 

 

 

NET "PMBUS_ALERT_LS"

LOC = "AH9";

## 2

on Q15

NET "PMBUS_CLK_LS"

LOC = "AC10";

## 2

on Q18

NET "PMBUS_CTRL_LS"

LOC = "AJ9";

## 2

on Q16

88

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ML605 Hardware User Guide

 

 

UG534 (v1.2.1) January 21, 2010

Page 87 Page 89
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Page 87 Page 89
Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch PinUsersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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