Xilinx ML605 manual Configuration Options

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Configuration Options

Configuration Options

The FPGA on the ML605 Evaluation Board can be configured by the following methods:

•“3. 128 Mb Platform Flash XL,” page 20

•“4. 32 MB Linear BPI Flash,” page 20

•“5. System ACE CF and CompactFlash Connector”

•“6. USB JTAG,” page 26

For more information, see the Virtex-6 FPGA Configuration User Guide at

http://www.xilinx.com/support/documentation/user_guides/ug360.pdf.

Table 1-32:Mode Switch S2 Settings

Mode Pins (M2,M1,M0)	Configuration Mode

110	Slave SelectMAP

010	BPI Mode

101	JTAG

With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream from either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket U73, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1. With no CF card present, the ML605 can be configured via the onboard JTAG controller and USB download cable as described above.

With the mode set to either Slave SelectMAP 110, or BPI Mode 010, the FPGA will attempt to configure itself from the selected Flash device as described in “3. 128 Mb Platform Flash XL,” page 20.

Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.

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UG534 (v1.2.1) January 21, 2010

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Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUsersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References