Xilinx ML605 manual 14IIC Bus Topology

Page 43

Detailed Description

U1

BANK 34

IIC_SDA_MAIN_LS IIC_SCL_MAIN_LS IIC_SDA_SFP

FPGA IIC INTERFACE	BANK 13
	BANK 34

	BANK 33

J63

FMC LPC

COLUMN C

2 Kb EEPROM on

any FMC LPC

Mezzanine Card Addr: 0b1010001

P3

DVI CONN

Addr: 0b1010000

U38

DVI CODEC

CHRONTEL

CH730C-TF

Addr: 0b1110110

IIC_SCL_SFP

IIC_SDA_DVI

IIC_SCL_DVI

FMC_LPC_IIC_SDA_LS

FMC_LPC_IIC_SCL_LS

LEVEL LEVEL

SHIFTER SHIFTER

FMC_LPC_IIC_SCL

FMC_LPC_IIC_SDA

IIC_CLK_DVI_F

IIC_SDA_DVI_F

LEVEL

SHIFTER

LEVEL

SHIFTER

IIC_SCL_MAIN

IIC_SDA_MAIN

SFP_MOD_DEF2

SFP_MOD_DEF1

U6

ST MICRO

M24C08-WDW6TP

Addr: 0b1010100 through

0b1010111

J64

FMC HPC

COLUMN C

2 Kb EEPROM on

any FMC LPC

Mezzanine Card

Addr: 0b1010000

J1

DDR3 SODIMM

SOCKET

Addr: 0b1010011 2 Kb EEPROM Addr: 0b0011011 Temperature Sensor

P4

SFP MODULE

CONNECTOR

Addr: 0b1010000

UG534_14_092109

Figure 1-14:IIC Bus Topology

ML605 Hardware User Guide	www.xilinx.com	43
UG534 (v1.2.1) January 21, 2010

Image 43

Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardIIC Eeprom 1 KB FeaturesML605 Evaluation Board SMAFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramDDR3 Sodimm ML605 FeaturesFeature Detailed DescriptionSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration3Voltage Rails U1 Fpga Bank 2Virtex-6 Fpga Configuration Modes M20Voltage Rails Cclk Direction4DDR3 Sodimm Connections MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank VCC1V5FPGADDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD3 DQ3 FLASHD0 DQ0FLASHD1 DQ1 FLASHD2 DQ2Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections GTXE1X0Y6 AA3 PCIERX7PAA4 PCIERX7N PCIE100MMGT0PSFP Module Connector Bit2 Bit1 Bit0 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYU80 M88E1111 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation 13Ethernet PHYConnections U1 Fpga PinRXD5 PHYRXD4RXD4 PHYRXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpgainitb User I/OFpga Init and Done LEDs Controlled LEDUser LEDs 18User LEDs and Gpio Connector, Directional LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUsersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08N FMCHPCHB09NFMCHPCHB08P FMCHPCHB13PDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFBM2C VadjVIOBM2C Vadj VREFAM2C VadjVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationUCD7230RGWR UCD9240PFCVccintfpga Vccaux29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References