Xilinx ML605 manual 30VITA 57.1 FMC LPC Connections, LPC Pin

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Chapter 1: ML605 Evaluation Board

Table 1-30shows the VITA 57.1 FMC LPC connections. The connector pinout is in

Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout.”

Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table..

Table 1-30:VITA 57.1 FMC LPC Connections

J63 FMC	Schematic Net Name	U1 FPGA		J63 FMC	Schematic Net Name	U1 FPGA
LPC Pin	Schematic Net Name	Pin		LPC Pin	Schematic Net Name	Pin
LPC Pin		Pin		LPC Pin		Pin

C2	FMC_LPC_DP0_C2M_P	D1		D4	FMC_LPC_GBTCLK0_M2C_P	M6

C3	FMC_LPC_DP0_C2M_N	D2		D5	FMC_LPC_GBTCLK0_M2C_N	M5

C6	FMC_LPC_DP0_M2C_P	G3		D8	FMC_LPC_LA01_CC_P	F31

C7	FMC_LPC_DP0_M2C_N	G4		D9	FMC_LPC_LA01_CC_N	E31

C10	FMC_LPC_LA06_P	K33		D11	FMC_LPC_LA05_P	H34

C11	FMC_LPC_LA06_N	J34		D12	FMC_LPC_LA05_N	H33

C14	FMC_LPC_LA10_P	F30		D14	FMC_LPC_LA09_P	L25

C15	FMC_LPC_LA10_N	G30		D15	FMC_LPC_LA09_N	L26

C18	FMC_LPC_LA14_P	C33		D17	FMC_LPC_LA13_P	D34

C19	FMC_LPC_LA14_N	B34		D18	FMC_LPC_LA13_N	C34

C22	FMC_LPC_LA18_CC_P	L29		D20	FMC_LPC_LA17_CC_P	N28

C23	FMC_LPC_LA18_CC_N	L30		D21	FMC_LPC_LA17_CC_N	N29

C26	FMC_LPC_LA27_P	R31		D23	FMC_LPC_LA23_P	R28

C27	FMC_LPC_LA27_N	R32		D24	FMC_LPC_LA23_N	R27

				D26	FMC_LPC_LA26_P	L33

				D27	FMC_LPC_LA26_N	M32


G2	FMC_LPC_CLK1_M2C_P	F33		H2	FMC_LPC_PRSNT_M2C_L	AD9

G3	FMC_LPC_CLK1_M2C_N	G33		H4	FMC_LPC_CLK0_M2C_P	A10

G6	FMC_LPC_LA00_CC_P	K26		H5	FMC_LPC_CLK0_M2C_N	B10

G7	FMC_LPC_LA00_CC_N	K27		H7	FMC_LPC_LA02_P	G31

G9	FMC_LPC_LA03_P	J31		H8	FMC_LPC_LA02_N	H30

G10	FMC_LPC_LA03_N	J32		H10	FMC_LPC_LA04_P	K28

G12	FMC_LPC_LA08_P	J30		H11	FMC_LPC_LA04_N	J29

G13	FMC_LPC_LA08_N	K29		H13	FMC_LPC_LA07_P	G32

G15	FMC_LPC_LA12_P	E32		H14	FMC_LPC_LA07_N	H32

G16	FMC_LPC_LA12_N	E33		H16	FMC_LPC_LA11_P	D31

G18	FMC_LPC_LA16_P	A33		H17	FMC_LPC_LA11_N	D32

G19	FMC_LPC_LA16_N	B33		H19	FMC_LPC_LA15_P	C32

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		UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch PinUsersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References