Xilinx ML605 manual 29System Monitor External Reference

Page 68

Chapter 1: ML605 Evaluation Board

22. System Monitor

The System Monitor provides information regarding the FPGA on-chip temperature and power supply conditions via JTAG and an internal FPGA interface. The System Monitor can also be used to monitor external analog signals via 17 external analog input channels. For more information regarding this functionality, which is featured on every Virtex-6 family member, see http://www.xilinx.com/systemmonitor.

This section provides a brief overview of the System Monitor related functionality that is supported on the ML605.

Reference and Power Supply

The System Monitor has dedicated analog power supply pins and supports the use of an external 1.25V reference IC (U23) for the analog-to-digital conversion process. An option (using jumper J19) to select an on-chip reference is also provided; however, the highest accuracy over a temperature range of -40°C to +125°C is obtained using an external reference. Figure 1-29illustrates the power supply and reference options on the ML605. For a more detailed discussion of these requirements, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]

VCC2V5

Analog Supply Filter

1

2

SYSMON_AVDD

VCC5

1

IN

C190

X5R

6.3V

1UF

U23

REF3012

REF3012AIDBZT

GND

C78

X5R

10V J19 0.1UF

3

2

AGND

1

21.25V

OUT

SYSMON_VREFP

C383

X5R

10V

0.1UF

Ferrie Bead

C191		3	C79
X5R			X5R
X5R			X5R
6.3V			10V
1UF			0.1UF

AGND

		Jumper on pins 1-2
		Default Setting:
		1-2 Select External Reference
GND	AGND	2-3 Select On-Chip Reference
		UG534_29_081209

Figure 1-29:System Monitor External Reference

68	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 68

Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmWDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkp SMA PinSmarefclkn Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsGpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin User DIP Switch Switch PinUsersmagpiop User SMA GpioUsersmagpion LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References