Xilinx ML605 manual Bank

Page 72

Chapter 1: ML605 Evaluation Board

FPGA Power Supply Margining

The PMBus (IIC), which provides access to the 2 x UDC9240 power controllers, can also be accessed via FPGA I/O in addition to a dedicated header (J3), see Figure 1-33. A full description of the UDC9240 functionality is outside the scope of this user guide. However, this useful feature can be used, for example, to margin the FPGA and board power supplies when evaluating a design. The System Monitor provides accurate measurements of the on-chip supply voltages as the FPGA supplies are margined. The PMBus (and fan) connections are shown in Figure 1-33.

TI_V3P3

PMBus Connector			R301	R299
	J3		R301	R299
	J3		100K	100K
			5%	5%
NC	1	2	NC
NC	3	4	NC
NC	5	6

78

910

DGND1

9240

R300	UDC9240
100K	UDC9240
5%

PMBUS_ALERT 35

PMBUS_DATA 20

PMBUS_CLK 19

PMBUS_CTRL 36

R335

1.0M

5%

AGND1

BANK 34

6vlx240tff1156

IO_L11N_SRCC_34_AJ9

IO_L11P_SRCC_34_AH9

IO_L10N_MRCC_34_AB10

IO_L10P_MRCC_34_AC10

IO_L9N_MRCC_34_M10

IO_L9P_MRCC_34_L10

AJ9	PMBUS_CTRL_LS
AH9	PMBUS_ALERT_LS
AB10	PMBUS_DATA_LS
AC10	PMBUS_CLK_LS
M10	SM_FAN_TACH
L10	SM_FAN_PWM

UG534_35_081209

Figure 1-33:UDC9240 PMBus Access

System Monitor ML605 Demonstration Design

The various features described in this section are easily evaluated using a MicroBlaze™ based reference designed provided with the ML605 Evaluation Board. This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies, temperature, and power consumption. In addition, the UART interface can be used to margin the FPGA supplies over the PMBus.

The System Monitor functionality can also be accessed at any time via JTAG using the ChipScope Pro Analyzer tool without design modifications or cores inserted into a user design. The ChipScope Pro Analyzer tool automatically connects to the System Monitor via a JTAG cable after a connection is established.

References

For more information on using the System Monitor and an overview of the tool support for this feature, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]

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		UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch PinUser SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References