Xilinx ML605 manual About This Guide

Page 5

Preface

About This Guide

This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools.

Guide Contents

This manual contains the following chapters:

•Chapter 1, “ML605 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the ML605 board.

•Appendix A, “Default Switch and Jumper Settings.”

•Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout.”

•Appendix C, “ML605 Master UCF.”

•Appendix D, “References.”

Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/support/documentation/virtex-6.htm.

•Virtex-6 Family Overview

The features and product selection of the Virtex-6 family are outlined in this overview.

•Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family.

•Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

•Virtex-6 FPGA Configuration Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

•Virtex-6 FPGA Clocking Resources User Guide

This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs.

ML605 Hardware User Guide	www.xilinx.com	5
UG534 (v1.2.1) January 21, 2010

Image 5

Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmWDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkp SMA PinSmarefclkn ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsGpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin Switch Pin User DIP SwitchUsersmagpiop User SMA GpioUsersmagpion J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References