Xilinx ML605 manual SMA Pin, Smarefclkn, Smarefclkp

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Chapter 1: ML605 Evaluation Board

GTX SMA Clock

The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in Figure 1-9and Table 1-7.

J30 32K10K-400E3

GND1

GND2 GND3

2

3

4

SMA_REFCLK_N

C61 1

0.1UF

2
10V	X5R

SMA_REFCLK_C_N1

SIG GND4 5 GND5 6 GND6 7 GND7 8

SMA_REFCLK_P

C62 1

0.1UF

2
10V	X5R

SMA_REFCLK_C_P1

J31 32K10K-400E3

		2
	GND1	2
	GND1	3
	GND2	3
	GND2	4
	GND3	4
SIG	GND3	5
	GND4	5
	GND4	6
	GND5	6
	GND5	7
	GND6	7
	GND6	8
	GND7	8
	GND7

UG534_09_081309

Figure 1-9:GTX SMA Clock

Table 1-7:GTX SMA Clock Connections

U1 FPGA Pin	Schematic Net Name	SMA Pin

F5	SMA_REFCLK_N	J30.1

F6	SMA_REFCLK_P	J31.1

30	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationSMA FeaturesML605 Evaluation Board IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramDetailed Description ML605 FeaturesFeature DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 FpgaCclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga BankVCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit013Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111PHYRXD5 PHYRXD4RXD4 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsControlled LED User I/OFpga Init and Done LEDs Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch PinUser SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsVccaux UCD9240PFCVccintfpga UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References