Xilinx manual 1ML605 High-Level Block Diagram

Page 10

Chapter 1: ML605 Evaluation Board

Block Diagram

Figure 1-1shows a high-level block diagram of the ML605 and its peripherals.

System ACE CF

 

 

 

JTAG USB Mini-B

S.A. CompactFlash

 

 

 

USB JTAG Circuit

S.A. 8-bit MPU I/F

 

 

 

 

 

 

 

 

 

VITA 57.1 FMC HPC Connector

VITA 57.1 FMC LPC Connector

Platform Flash

Linear BPI Flash

DVI Codec

VGA Video

DVI Video Connector

10/100/1000 Ethernet PHY MII/GMII/RMII

SODIMM Socket

204-pin, DDR3

Decoupling Caps

BANK32

BANK12, 13

BANK15,16

BANK24

BANK14,22

BANK34,116

BANK23,24

 

BANK34

 

BANK112,113

BANK0

 

BANK32

 

BANK33

 

 

BANK34

 

Virtex-6

 

 

 

FPGA

 

 

XC6VLX240T - 1FFG1156

 

BANK33

 

BANK116

 

BANK 25, 35

 

BANK114

BANK 26, 36

 

BANK115

BANK14, 33, 36 BANK24,34

BANK14

BANK24

SYSMON I/F

INIT, DONE LEDs

PROG PB, MODE SW

IIC Bus

IIC EEPROM

FMC HPC

DDR3 SODIMM IIC

FMC LPC

SFP Module

Connector

SGMII

PCIe X8 Edge Connector

MGT SMA REF Clock

MGT RX/TX SMA Port

MEM Vterm

Regulator

User LED/SW

User DIP SW

User LCD

200 MHz LVDS Clock

SMA Clock

User S.E. 2.5V Clock

USB Controller

Host Type “A”

Peripheral Mini-B

Connectors

CP2103 USB-TO-UART

Bridge

USB Mini-B

UG534_01_092709

Figure 1-1:ML605 High-Level Block Diagram

Related Xilinx Documents

Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources. See Appendix D, “References” for a direct link to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions:

•ISE: www.xilinx.com/ise

•EDK: www.xilinx.com/edk

•Intellectual Property: www.xilinx.com/ipcenter

•Answer Browser: www.xilinx.com/support

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www.xilinx.com

ML605 Hardware User Guide

 

 

UG534 (v1.2.1) January 21, 2010

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Page 9 Page 11
Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationSMA FeaturesML605 Evaluation Board IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramDetailed Description ML605 FeaturesFeature DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 FpgaCclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga BankVCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit013Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111PHYRXD5 PHYRXD4RXD4 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsControlled LED User I/OFpga Init and Done LEDs Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch PinUsersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsVccaux UCD9240PFCVccintfpga UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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