Xilinx ML605 manual Sgmii GTX Transceiver Clock Generation, 13Ethernet PHYConnections U1 Fpga Pin

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							Detailed Description

			Table 1-12:Board Connections for PHY Configuration Pins (Cont’d)

			Pin	Connection on	Bit[2]	Bit[1]	Bit[0]
			Pin	Board	Definition and Value	Definition and Value	Definition and Value
				Board	Definition and Value	Definition and Value	Definition and Value

			CFG5	VCC 2.5V	DIS_FC = 1	DIS_SLEEP = 1	HWCFG_MD[3] = 1
			CFG6	PHY_LED_RX	SEL_BDT = 0	INT_POL = 1	75/50 OHM = 0

SGMII GTX Transceiver Clock Generation

An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125- MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode voltage.

C348		33PF		50V	NPO
1		33PF		2
1				2
C347		33PF		50V	NPO
C347				50V	NPO
1				2
1				2

1R132 DNP 1%

21/16W

VDDA_SGMIICLK

VDD_SGMIICLK

ICS84402II

1

VDDA

VDD

8

SGMIICLK_QO_C_P

X3

2

GND

Q0

7

SGMIICLK_XTAL_OUT

3

XTAL_OUT

NQ0

6

SGMIICLK_QO_C_N

SGMIICLK_XTAL_IN

4

XTAL_IN

OE

5

U82

25.000MHZ

GND_SGMIICLK

125.00 MHz Clock

C55 1 C56 1

0.1UF 0.1UF

	2

	10V	X5R



	2
	2

	10V	X5R
	10V	X5R

SGMIICLK_QO_P

SGMIICLK_QO_N

UG534_13_111709

Figure 1-13:Ethernet SGMII Clock - 125 MHz

Table 1-13shows the connections and pin numbers for the PHY.

Table 1-13:Ethernet PHYConnections

	U1 FPGA Pin	Schematic Net Name	U80 M88E1111

			Pin Number	Pin Name
			Pin Number	Pin Name

	AN14	PHY_MDIO	33	MDIO

	AP14	PHY_MDC	35	MDC

	AH14	PHY_INT	32	INT_B

	AH13	PHY_RESET	36	RESET_B

	AL13	PHY_CRS	115	CRS

	AK13	PHY_COL	114	COL

	AP11	PHY_RXCLK	7	RXCLK

	AG12	PHY_RXER	8	RXER

	AM13	PHY_RXCTL_RXDV	4	RXDV

	AN13	PHY_RXD0	3	RXD0

	AF14	PHY_RXD1	128	RXD1

	AE14	PHY_RXD2	126	RXD2

	AN12	PHY_RXD3	125	RXD3

ML605 Hardware User Guide	www.xilinx.com	37
UG534 (v1.2.1) January 21, 2010

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Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUsersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References