Xilinx manual ML605 Master UCF

Page 79

Appendix C

ML605 Master UCF

The UCF template is provided for designs that target the ML605. Net names provided in the constraints below correlate with net names on the ML605 Rev. D schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information.

Users can refer to the UCF files generated by tools such as MIG (Memory Interface Generator for memory interfaces) and BSB (Base System Builder) for more detailed information concerning the I/O standards required for each particular interface. The FMC connectors J63 and J64 are connected to 2.5V Vcco banks. Because each user’s FMC card implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each customer.

NET "CLK_33MHZ_SYSACE"

LOC = "AE16";

## 93

on U19

NET "CPU_RESET"

LOC = "H10";

## 2

on SW10 pushbutton (active-High)

##

 

 

 

NET "DDR3_A0"

LOC = "L14";

## 98

on J1

NET "DDR3_A1"

LOC = "A16";

## 97

on J1

NET "DDR3_A2"

LOC = "B16";

## 96

on J1

NET "DDR3_A3"

LOC = "E16";

## 95

on J1

NET "DDR3_A4"

LOC = "D16";

## 92

on J1

NET "DDR3_A5"

LOC = "J17";

## 91

on J1

NET "DDR3_A6"

LOC = "A15";

## 90

on J1

NET "DDR3_A7"

LOC = "B15";

## 86

on J1

NET "DDR3_A8"

LOC = "G15";

## 89

on J1

NET "DDR3_A9"

LOC = "F15";

## 85

on J1

NET "DDR3_A10"

LOC = "M16";

## 107

on J1

NET "DDR3_A11"

LOC = "M15";

## 84

on J1

NET "DDR3_A12"

LOC = "H15";

## 83

on J1

NET "DDR3_A13"

LOC = "J15";

## 119

on J1

NET "DDR3_A14"

LOC = "D15";

## 80

on J1

NET "DDR3_A15"

LOC = "C15";

## 78

on J1

NET "DDR3_BA0"

LOC = "K19";

## 109 on J1

NET "DDR3_BA1"

LOC = "J19";

## 108

on J1

NET "DDR3_BA2"

LOC = "L15";

## 79

on J1

NET "DDR3_CAS_B"

LOC = "C17";

## 115

on J1

NET "DDR3_CKE0"

LOC = "M18";

## 73

on J1

NET "DDR3_CKE1"

LOC = "M17";

## 74

on J1

NET "DDR3_CLK0_N"

LOC = "H18";

## 103 on J1

NET "DDR3_CLK0_P"

LOC = "G18";

## 101 on J1

NET "DDR3_CLK1_N"

LOC = "L16";

## 104 on J1

NET "DDR3_CLK1_P"

LOC = "K16";

## 102

on J1

NET "DDR3_D0"

LOC = "J11";

## 5

on J1

NET "DDR3_D1"

LOC = "E13";

## 7

on J1

NET "DDR3_D2"

LOC = "F13";

## 15

on J1

NET "DDR3_D3"

LOC = "K11";

## 17

on J1

NET "DDR3_D4"

LOC = "L11";

## 4

on J1

NET "DDR3_D5"

LOC = "K13";

## 6

on J1

NET "DDR3_D6"

LOC = "K12";

## 16

on J1

NET "DDR3_D7"

LOC = "D11";

## 18

on J1

ML605 Hardware User Guide

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UG534 (v1.2.1) January 21, 2010

 

 

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Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardIIC Eeprom 1 KB FeaturesML605 Evaluation Board SMAFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramDDR3 Sodimm ML605 FeaturesFeature Detailed DescriptionSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration3Voltage Rails U1 Fpga Bank 2Virtex-6 Fpga Configuration Modes M20Voltage Rails Cclk Direction4DDR3 Sodimm Connections MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank VCC1V5FPGADDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD3 DQ3 FLASHD0 DQ0FLASHD1 DQ1 FLASHD2 DQ2Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections GTXE1X0Y6 AA3 PCIERX7PAA4 PCIERX7N PCIE100MMGT0PSFP Module Connector Bit2 Bit1 Bit0 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYU80 M88E1111 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation 13Ethernet PHYConnections U1 Fpga PinRXD5 PHYRXD4RXD4 PHYRXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpgainitb User I/OFpga Init and Done LEDs Controlled LEDUser LEDs 18User LEDs and Gpio Connector, Directional LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUsersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08N FMCHPCHB09NFMCHPCHB08P FMCHPCHB13PDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFBM2C VadjVIOBM2C Vadj VREFAM2C VadjVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationUCD7230RGWR UCD9240PFCVccintfpga Vccaux29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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