Xilinx ML605 manual System Monitor Header J35

Page 69

Detailed Description

System Monitor Header (J35)

Figure 1-30shows the pinout for the System Monitor 12-pin header. The header provides user access to the analog power supply (AVdd) and the 1.25V reference shown in Figure 1-29, page 68. Access to the FPGA thermal diode and dedicated analog input channel (Vp/Vn) is also provided on this header. The header can be used to connect user specific analog signals and sensors to the system monitor.

The kelvin points for a 5 milliohm current sensing shunt in the FPGA 1V Vccint core supply are also available on this header. By connecting header pins 9 to 11 and 10 to 12 using

jumpers, the system monitor can be used to monitor the FPGA core current and power consumption. This can be used to collect useful power information about a particular design or implementation.

Anti-alias Filter

SYSMON_VN

R232

100 1%

1/16W

 

 

 

C169

R233

100 1%

1/16W

16V

X7R

 

 

 

SYSMON_VP

0.01UF

Dedicated Analog Inputs

 

 

System Monitor

 

 

FPGA

 

 

 

 

Thermal Diode

 

 

Header J35

 

 

 

 

 

 

access

 

 

 

 

NC

1

2

 

FPGA_DX_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

3

4

 

FPGA_DX_N

 

 

 

 

 

 

5

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V Reference

 

7

8

 

SYSMON_AVDD

 

 

 

 

 

 

 

 

 

 

 

9

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vccint_shunt_N

 

11

12

 

Vccint_shunt_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AGND

To Measure VCCINT Current:

Jumper on 9-11, 10-12

Connect Vccint shunt to Vp,Vn

UG534_37 _081209

Figure 1-30:System Monitor Header (J35)

ML605 Hardware User Guide

www.xilinx.com

69

UG534 (v1.2.1) January 21, 2010

 

 

Page 68 Page 70
Image 69
Page 68 Page 70
Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSMA Pin SmarefclknSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUser SMA Gpio UsersmagpionUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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