Xilinx ML605 manual Mb Platform Flash XL, MB Linear BPI Flash

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Chapter 1: ML605 Evaluation Board

3. 128 Mb Platform Flash XL

A 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard 47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification. This allows the PCIe interface to be recognized and enumerated when plugged into a host PC.

To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the FPGA is used for configuration. Configuration DIP switch S2, switch 1, controls the 47 MHz oscillator enable as outlined in “18. Switches,” page 53.

See S2 switch setting details in Table 1-26, page 56. Also, see the “FPGA Design Considerations for the Configuration Flash,” page 23 for FPGA design recommendations.

4. 32 MB Linear BPI Flash

A Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL.

The P30_CS net is used to select the P30 or the XCF128. Power-on configuration is selected by the P30_CS net which is tied to a dip switch S2 (selects pullup/pulldown) and is also wired to an FPGA non-config pin. The dip switch allows power selection for the configuration device P30 or XCF128XL. The dip switch selection can be overridden by the FPGA after configuration by controlling the logic level of the P30_CS signal.

See S2 switch setting details in Table 1-26, page 56. For an overview on configuring the FPGA, see “Configuration Options,” page 73.

Figure 1-3shows a block diagram for the Platform Flash and BPI Flash.

FPGA U1 Bank 34

FLASH_A[22:0]

U27

PLATFORM

FLASH

A D

 

 

 

 

S1 Switch 4

 

 

 

 

OFF = Disable System ACE,

 

 

 

 

 

enable U4/U27 flash boot

 

 

 

 

ON = Enable System ACE boot when

FLASH_D[15:0]

 

 

CF card is present

FPGA U1

VCC2V5

Bank 24

 

 

 

 

U10

 

 

 

6

 

 

S2 SWITCH 6

ON = U4 BPI Upper Half

OFF = U4 BPI Lower Half

FLASH_A[23]

FPGA U1

Bank 24

VCC2V5

510S2-6 7 6

4.7K

CE

U4

BPI

FLASH

AD

A23 E

 

 

PLATFLASH_FCS_B

 

 

 

 

P30_CS_SEL

 

 

 

 

 

 

 

VCC2V5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(FPGA U1 pin AJ12)

 

 

 

 

 

 

 

 

 

 

 

510 S2-2

2

1

 

 

 

 

 

 

 

11

 

 

 

S2 SWITCH 2

 

 

 

 

 

 

 

 

 

 

 

 

4.7K

 

 

 

ON = U4 BOOT

 

 

 

 

 

 

 

OFF = U27 BOOT

 

 

 

 

 

 

 

 

 

 

VCC2V5

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

3 FPGA_FCS_B FPGA U1

 

 

 

 

 

 

 

 

 

FLASH_CE_B

 

 

 

 

 

Bank 24

 

 

 

 

 

 

 

 

 

 

UG534_03_011110

Figure 1-3:Platform Flash and BPI Flash Block Diagram

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ML605 Hardware User Guide

 

 

UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmWDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkp SMA PinSmarefclkn Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsGpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin User DIP Switch Switch PinUsersmagpiop User SMA GpioUsersmagpion LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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