Xilinx ML605 manual Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout

Page 77

Appendix B

VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout

Figure B-1shows the pinout of the FMC LPC connector. Pins marked NC are not connected.

	K	J	H	G	F	E	D	C	B	A
1	NC	NC	VR EF_A_M2C	GND	NC	NC	P G_C2M	G ND	NC	NC
2	NC	NC	PR SNT_M2C_L	C LK1_M2C_P	NC	NC	G ND	DP 0_C2M_P	NC	NC
3	NC	NC	GND	C LK 1_M2C_N	NC	NC	G ND	DP 0_C2M_N	NC	NC
4	NC	NC	CLK0_M2C _P	GND	NC	NC	G BTCLK0_M2C _P	GND	NC	NC
5	NC	NC	CLK0_M2C _N	GND	NC	NC	G BTCLK0_M2C _N	GND	NC	NC
6	NC	NC	GND	LA00_P _C C	NC	NC	G ND	DP 0_M2C_P	NC	NC
7	NC	NC	LA02_P	LA00_N_C C	NC	NC	G ND	DP 0_M2C_N	NC	NC
8	NC	NC	LA02_N	GND	NC	NC	LA01_P _C C	G ND	NC	NC
9	NC	NC	GND	LA03_P	NC	NC	LA01_N_C C	G ND	NC	NC
10	NC	NC	LA04_P	LA03_N	NC	NC	GND	LA06_P	NC	NC
11	NC	NC	LA04_N	GND	NC	NC	LA05_P	LA06_N	NC	NC
12	NC	NC	G ND	LA08_P	NC	NC	LA05_N	GND	NC	NC
13	NC	NC	LA07_P	LA08_N	NC	NC	GND	G ND	NC	NC
14	NC	NC	LA07_N	GND	NC	NC	LA09_P	LA10_P	NC	NC
15	NC	NC	G ND	LA12_P	NC	NC	LA09_N	LA10_N	NC	NC
16	NC	NC	LA11_P	LA12_N	NC	NC	GND	G ND	NC	NC
17	NC	NC	LA11_N	GND	NC	NC	LA13_P	GND	NC	NC
18	NC	NC	G ND	LA16_P	NC	NC	LA13_N	LA14_P	NC	NC
19	NC	NC	LA15_P	LA16_N	NC	NC	GND	LA14_N	NC	NC
20	NC	NC	LA15_N	GND	NC	NC	LA17_P _C C	G ND	NC	NC
21	NC	NC	G ND	LA20_P	NC	NC	LA17_N_C C	G ND	NC	NC
22	NC	NC	LA19_P	LA20_N	NC	NC	GND	LA18_P _C C	NC	NC
23	NC	NC	LA19_N	GND	NC	NC	LA23_P	LA18_N_C C	NC	NC
24	NC	NC	G ND	LA22_P	NC	NC	LA23_N	GND	NC	NC
25	NC	NC	LA21_P	LA22_N	NC	NC	GND	G ND	NC	NC
26	NC	NC	LA21_N	GND	NC	NC	LA26_P	LA27_P	NC	NC
27	NC	NC	G ND	LA25_P	NC	NC	LA26_N	LA27_N	NC	NC
28	NC	NC	LA24_P	LA25_N	NC	NC	GND	G ND	NC	NC
29	NC	NC	LA24_N	GND	NC	NC	TCK	GND	NC	NC
30	NC	NC	G ND	LA29_P	NC	NC	TDI	S CL	NC	NC
31	NC	NC	LA28_P	LA29_N	NC	NC	TDO	S DA	NC	NC
32	NC	NC	LA28_N	GND	NC	NC	3P3VAUX	GND	NC	NC
33	NC	NC	G ND	LA31_P	NC	NC	TMS	G ND	NC	NC
34	NC	NC	LA30_P	LA31_N	NC	NC	TR ST_L	GA0	NC	NC
35	NC	NC	LA30_N	GND	NC	NC	G A1	12P0V	NC	NC
36	NC	NC	G ND	LA33_P	NC	NC	3P 3V	GND	NC	NC
37	NC	NC	LA32_P	LA33_N	NC	NC	GND	12P0V	NC	NC
38	NC	NC	LA32_N	GND	NC	NC	3P3V	G ND	NC	NC
39	NC	NC	G ND	VADJ	NC	NC	GND	3P3V	NC	NC
40	NC	NC	VADJ	G ND	NC	NC	3P 3V	GND	NC	NC

Figure B-1:FMC LPC Connector Pinout

ML605 Hardware User Guide	www.xilinx.com	77
UG534 (v1.2.1) January 21, 2010

Image 77

Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmWDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSmarefclkp SMA PinSmarefclkn ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsGpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin Switch Pin User DIP SwitchUsersmagpiop User SMA GpioUsersmagpion J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References